H01L21/326

Electrically or temperature activated shape-memory materials for warpage control
10861797 · 2020-12-08 · ·

A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.

Symmetrical plural-coil plasma source with side RF feeds and RF distribution plates

A plasma reactor has an overhead inductively coupled plasma source with two coil antennas and symmetric and radial RF feeds and cylindrical RF shielding around the symmetric and radial RF feeds. The radial RF feeds are symmetrically fed to the plasma source.

Plasma processing apparatus and plasma processing method

A plasma processing apparatus includes a processing chamber including a dielectric window; a coil shaped RF antenna provided outside the dielectric window; a substrate supporting unit, provided in the processing chamber, for mounting thereon a target substrate to be processed; a processing gas supply unit for supplying a desired processing gas to the processing chamber to perform a desired plasma process on the target substrate; and an RF power supply unit for supplying an RF power to the RF antenna to generate a plasma of the processing gas by an inductive coupling in the processing chamber. The apparatus further includes a floating coil electrically floated and arranged at a position outside the processing chamber where the floating coil is to be coupled with the RF antenna by an electromagnetic induction; and a capacitor provided in a loop of the floating coil.

Porous silicon relaxation medium for dislocation free CMOS devices

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

Porous silicon relaxation medium for dislocation free CMOS devices

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

ACTIVE MATRIX SUBSTRATE, OPTICAL SHUTTER SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE
20200312888 · 2020-10-01 ·

An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.

Silicide implants

The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.

Silicide implants

The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.

Process of making a short-circuited diode that prevents electrocution
10756201 · 2020-08-25 ·

A process of making a short-circuited diode that changes the properties of an electric current that passes through the short-circuited diode so that the current does not harm a human that contacts the current after it passes through the diode.

Process of making a short-circuited diode that prevents electrocution
10756201 · 2020-08-25 ·

A process of making a short-circuited diode that changes the properties of an electric current that passes through the short-circuited diode so that the current does not harm a human that contacts the current after it passes through the diode.