A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

An array substrate according to the present invention is a TFT substrate including a pixel TFT and a drive TFT on a substrate, where the pixel TFT includes a first source electrode, a first drain electrode, and an amorphous silicon layer, and the drive TFT includes a third oxide semiconductor layer provided on a gate insulating film while overlapping a second gate electrode in plan view, and a second source electrode and a second drain electrode overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.

Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

Various embodiments relate to an oxide semiconductor having improved resistance through cation/anion substitutional doping, and a manufacturing method therefor, in which: an IGZO channel layer is prepared; carrier diffusion is induced in the IGZO channel layer, by using a group 4 element or a group 7 element, so that carriers remain in the IGZO channel layer; and through carrier diffusion, low resistance contact with the IGZO channel layer can be implemented, with respect to a metal electrode. Various embodiments relate to a thin-film transistor having an ohmic junction structure of an oxide semiconductor, and a manufacturing method therefor. Provided are a thin-film transistor, and a manufacturing method therefor, the thin-film transistor comprising: a substrate; an IGZO channel layer which is disposed on the substrate and is divided into a first region and a second region that has at least one groove formed therein; a first electrode which is disposed on the first region of the IGZO channel layer; an ohmic junction layer which is made of an n+ oxide and is disposed in a groove; and a second electrode which is bonded on the ohmic junction layer.

The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

A method for manufacturing an array substrate, a display panel and a display device are provided. The method includes forming a semiconductor layer, a gate insulating layer, a gate and an inter-layer insulator successively on a base substrate; forming via holes in the inter-layer insulator so as to expose portions of the semiconductor layer; performing plasma bombardment to the portions of the semiconductor layer exposed in the via holes; forming a source electrode and a drain electrode coupled with the semiconductor layer through the via holes respectively on the inter-layer insulator.

A method for manufacturing an array substrate, a display panel and a display device are provided. The method includes forming a semiconductor layer, a gate insulating layer, a gate and an inter-layer insulator successively on a base substrate; forming via holes in the inter-layer insulator so as to expose portions of the semiconductor layer; performing plasma bombardment to the portions of the semiconductor layer exposed in the via holes; forming a source electrode and a drain electrode coupled with the semiconductor layer through the via holes respectively on the inter-layer insulator.

The present disclosure relates to an integrated chip device. The integrated chip device includes a plurality of conductive lines disposed over a substrate. The plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines. A ferroelectric layer is along sidewalls of the plurality of conductive lines and the dielectric layers. The ferroelectric layer separates a channel layer from the plurality of conductive lines. A species is disposed within the ferroelectric layer. The species has a concentration that decreases from the channel layer towards a surface of the ferroelectric layer that faces away from the channel layer.