Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same.

A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.

In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.

In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.

In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

Ion implantation or deposition can be used to modify the bulk electrical properties of topological insulators. More particularly, ion implantation or deposition can be used to compensate for the non-zero bulk conductivity due to extrinsic charge carriers. The direct implantation of deposition/annealing of dopants allows better control over carrier concentrations for the purposes of achieving low bulk conductivity. Ion implantation or deposition enables the fabrication of inhomogeneously doped structures, enabling new types of device designs.

Ion implantation or deposition can be used to modify the bulk electrical properties of topological insulators. More particularly, ion implantation or deposition can be used to compensate for the non-zero bulk conductivity due to extrinsic charge carriers. The direct implantation of deposition/annealing of dopants allows better control over carrier concentrations for the purposes of achieving low bulk conductivity. Ion implantation or deposition enables the fabrication of inhomogeneously doped structures, enabling new types of device designs.

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.