H01L21/423

Asymmetric high-k dielectric for reducing gate induced drain leakage

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Surface treatment process performed on devices for TFT applications

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

Surface treatment process performed on devices for TFT applications

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE
20180366565 · 2018-12-20 ·

A thin film transistor, a method for fabricating the same, a display panel and a display device are disclosed. The method includes forming an active layer on a substrate; forming an insulating layer on the active layer and an exposed surface of the substrate; forming a first conductive layer on the insulating layer; patterning the first conductive layer and the insulating layer to form a first stack on the active layer, wherein the first stack includes a first portion of the first conductive layer and a first portion of the insulating layer, the first stack acts as a gate stack and the active layer includes a channel region below the gate stack and a source region and a drain region at two sides of the channel region; and performing plasma treatment on the first conductive layer, the source region and the drain region, to improve conductivity.

THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE
20180366565 · 2018-12-20 ·

A thin film transistor, a method for fabricating the same, a display panel and a display device are disclosed. The method includes forming an active layer on a substrate; forming an insulating layer on the active layer and an exposed surface of the substrate; forming a first conductive layer on the insulating layer; patterning the first conductive layer and the insulating layer to form a first stack on the active layer, wherein the first stack includes a first portion of the first conductive layer and a first portion of the insulating layer, the first stack acts as a gate stack and the active layer includes a channel region below the gate stack and a source region and a drain region at two sides of the channel region; and performing plasma treatment on the first conductive layer, the source region and the drain region, to improve conductivity.

Thermal Neutron Transmutation Doped Gallium Oxide Semiconductor

A germanium (Ge)-doped gallium oxide (Ga.sup.2O.sup.3) semiconductor material and method of making are provided. In embodiments, a method of making the Ge-doped Ga.sup.2O.sup.3 semiconductor material includes: subjecting a Ga.sub.2O.sub.3 semiconductor material to neutron irradiation comprising a higher thermal neutron content than fast neutron content, thereby producing a Ge-doped Ga.sub.2O.sub.3 semiconductor material; and annealing the Ge-doped Ga.sub.2O.sub.3 semiconductor material at a temperature of at least 700? C. in an atmosphere of nitrogen gas, thereby generating an electrically conductive n-type Ge-doped Ga.sub.2O.sub.3 semiconductor material.

Thermal Neutron Transmutation Doped Gallium Oxide Semiconductor

A germanium (Ge)-doped gallium oxide (Ga.sup.2O.sup.3) semiconductor material and method of making are provided. In embodiments, a method of making the Ge-doped Ga.sup.2O.sup.3 semiconductor material includes: subjecting a Ga.sub.2O.sub.3 semiconductor material to neutron irradiation comprising a higher thermal neutron content than fast neutron content, thereby producing a Ge-doped Ga.sub.2O.sub.3 semiconductor material; and annealing the Ge-doped Ga.sub.2O.sub.3 semiconductor material at a temperature of at least 700? C. in an atmosphere of nitrogen gas, thereby generating an electrically conductive n-type Ge-doped Ga.sub.2O.sub.3 semiconductor material.

SURFACE TREATMENT PROCESS PERFOMRED ON DEVICES FOR TFT APPLICATIONS
20180261698 · 2018-09-13 ·

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

SURFACE TREATMENT PROCESS PERFOMRED ON DEVICES FOR TFT APPLICATIONS
20180261698 · 2018-09-13 ·

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
10008612 · 2018-06-26 · ·

The disclosure provides a method of manufacturing a thin film transistor on a base substrate by patterning an active layer comprising a metal oxynitride, and treating the active layer with a plasma comprising oxygen.