Patent classifications
H01L21/461
CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION FOR HIGH EFFECTIVE POLISHING OF SUBSTRATES COMPRISING GERMANIUM
Disclosed herein is a chemical mechanical polishing (CMP) composition (Q) containing (A) inorganic particles, (B) a compound of general formula (I) below, and (C) an aqueous medium, in which the composition (Q) has a pH of from 2 to 6.
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USE OF A CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION FOR POLISHING OF COBALT AND / OR COBALT ALLOY COMPRISING SUBSTRATES
Use of a chemical mechanical polishing (CMP) composition (Q) for chemical mechanical polishing of a substrate (S) comprising (i) cobalt and/or (ii) a cobalt alloy, wherein the CMP composition (Q) comprises (A) Inorganic particles (B) a triazine derivative of the general formula (I) wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5 and R.sup.6 are independently from each other H, methyl, ethyl, propyl, butyl, pentyl, C.sub.2-C.sub.10-alkylcarboxylic acid, hydroxymethyl, vinyl or allyl (C) at least one amino acid, (D) at least one oxidizer (E) an aqueous medium and wherein the CMP composition (Q) has a pH of from 7 to 10.
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USE OF A CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION FOR POLISHING OF COBALT AND / OR COBALT ALLOY COMPRISING SUBSTRATES
Use of a chemical mechanical polishing (CMP) composition (Q) for chemical mechanical polishing of a substrate (S) comprising (i) cobalt and/or (ii) a cobalt alloy, wherein the CMP composition (Q) comprises (A) Inorganic particles (B) a triazine derivative of the general formula (I) wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5 and R.sup.6 are independently from each other H, methyl, ethyl, propyl, butyl, pentyl, C.sub.2-C.sub.10-alkylcarboxylic acid, hydroxymethyl, vinyl or allyl (C) at least one amino acid, (D) at least one oxidizer (E) an aqueous medium and wherein the CMP composition (Q) has a pH of from 7 to 10.
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Substrate processing apparatus
A substrate processing apparatus has a cup part for receiving processing liquid such as pure water which is splashed from a substrate. The cup part is formed of electrical insulation material or semiconductor material. Hydrophilic treatment may be performed on an outer annular surface of the cup part and water may be held on the outer annular surface of the cup part while processing the substrate. With the disclosed apparatus, charged potential of the cup part generated by splashing of pure water can be suppressed, without greatly increasing the manufacturing cost of the substrate processing apparatus. As a result, it is possible to prevent electric discharge from occurring on the substrate due to induction charging of the substrate, in application of the processing liquid onto the substrate.
USE OF A CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION FOR POLISHING OF COBALT AND / OR COBALT ALLOY COMPRISING SUBSTRATES
A chemical mechanical polishing (CMP) composition (Q) for chemical mechanical polishing of a substrate (S) containing (i) cobalt and/or (ii) a cobalt alloy, wherein the CMP composition (Q) contains: (A) Inorganic particles, (B) a substituted aromatic compound with at least one carboxylic acid function as corrosion inhibitor, (C) at least one amino acid, (D) at least one oxidizer, (E) an aqueous medium, wherein the CMP composition (Q) has a pH of from 7 to 10.
Plasma processing method
Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.
Methods of manufacturing semiconductor devices
In a method of manufacturing a semiconductor device, a mask layer and a first layer may be sequentially formed on a substrate. The first layer may be patterned by a photolithography process to form a first pattern. A silicon oxide layer may be formed on the first pattern. A coating pattern including silicon may be formed on the silicon oxide layer. The mask layer may be etched using a second pattern as an etching mask to form a mask pattern, and the second pattern may includes the first pattern, the silicon oxide layer and the coating pattern. The mask pattern may have a uniform size.
Composition and process for selectively etching metal nitrides
A removal composition and process for selectively removing a first metal gate material (e.g., titanium nitride) relative to a second metal gate material (e.g., tantalum nitride) from a microelectronic device having said material thereon. The removal composition can include fluoride or alternatively be substantially devoid of fluoride. The substrate preferably comprises a high-k/metal gate integration scheme.
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first cover layer, where a first growth rate difference exists between growth rates of the first cover layer on the top surface of the stress layer and the first cover layer on a side surface of the stress layer. Further, the method includes forming a second cover layer, where a second growth rate difference exists between growth rates of the second cover layer on the top surface of the stress layer and the second cover layer on the side surface of the stress layer, and the second growth rate difference is larger than the first growth rate difference.
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first cover layer, where a first growth rate difference exists between growth rates of the first cover layer on the top surface of the stress layer and the first cover layer on a side surface of the stress layer. Further, the method includes forming a second cover layer, where a second growth rate difference exists between growth rates of the second cover layer on the top surface of the stress layer and the second cover layer on the side surface of the stress layer, and the second growth rate difference is larger than the first growth rate difference.