A ceramic article. In some embodiments, the ceramic article includes a ceramic body composed of a ceramic material; and a first conductive trace, the first conductive trace having a first portion entirely within the ceramic material, the first portion having a length of 0.5 mm and transverse dimensions less than 500 microns, the ceramic material including a plurality of ceramic particles in a ceramic matrix.

An electronic circuit has three circuit carriers and two semiconductor components. A first semiconductor component contacts with its upper side an underside of a first circuit carrier, and with its underside an upper side of a second circuit carrier. The first circuit carrier has vias, with a first via connecting the first semiconductor component to a first conducting path and a second via connecting a connection element forming a second conducting path providing an integral connection between the circuit carriers. A second semiconductor component contacts the underside of the first circuit carrier and is electrically connected to the first or second conducting path. An underside of the second semiconductor component contacts an upper side of the third circuit carrier. A lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of both the second and the third circuit carrier.

Provided are a semiconductor module in which bonding properties between an insulated substrate and a sealing resin is improved and a method for manufacturing the semiconductor module. A semiconductor module 50 is provided with: an insulated substrate 23; a circuit pattern 24 that is formed on the insulated substrate; semiconductor elements 25, 26 that are joined on the circuit pattern; and a sealing resin 28 for sealing the insulated substrate, the circuit pattern, and the semiconductor elements. The surface 23a of the insulated substrate in a part where the insulative substrate and the sealing resin are bonded to each other, is characterized in that, in a cross section of the insulated substrate, the average roughness derived in a 300-μm wide range is 0.15 μm or greater and the average roughness derived in a 3-μm-wide range is 0.02 μm or greater.

Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.

A wiring substrate includes a substrate body composed of a plurality of ceramic layers (insulating materials) and having a front surface and a back surface located on opposite sides thereof and having a side surface located between the front surface and the back surface. The outline of the substrate body in a plan view which is a view from the front surface side is composed of a plurality of curved portions separated from one another and a plurality of straight portions each located between adjacent ones of the curved portions. The total length of the curved portions in the plan view is at least 40% of the sum of the total length of the curved portions and the total length of the straight portions.

A method for producing a metal-ceramic substrate with a plurality of electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into a plurality of holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the plurality of holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.

A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development.

A semiconductor device includes a semiconductor chip, an insulated circuit board including a metal plate, an insulating plate and a circuit pattern, each of which has a rectangular shape, and a spacer part disposed on the periphery of a rear surface of the metal plate including at least one of the four corners thereof. The spacer part protrudes from a rear surface of the metal plate in the thickness direction away from a front surface of the insulated circuit board.

Provided is a semiconductor module, including: a semiconductor chip; a terminal, configured to extend in a extending direction, and be connected electrically with the semiconductor chip; a sealing resin, configured to seal the semiconductor chip, and cover at least a part of an upper surface of the terminal and at least a part of a lower surface of the terminal; and a lower side resin, configured to extend in the extending direction from the sealing resin, and cover at least a part of the lower surface of the terminal, wherein in the extending direction, a length at which the sealing resin and the lower side resin cover the lower surface of the terminal is greater than a length at which the sealing resin covers the upper surface of the terminal in the extending direction; and wherein the sealing resin and the lower side resin are formed of a same material.