Provided is a semiconductor device including: a laminated substrate in which a circuit layer, an insulating layer, and a metal layer are sequentially laminated. A slit is formed in the circuit layer. A recess recessed from one surface side facing the insulating layer toward the other surface side is formed in the metal layer. The recess of the metal layer has a relaxation portion at least partially overlapping the slit of the circuit layer in a planar view.

An insulated metal substrate (IMS) and a method for manufacturing the same are disclosed. The IMS includes an electrically conductive line pattern layer, an encapsulation layer, a first adhesive layer, a second adhesive layer, and a heat sink element. The encapsulation layer fills a gap between a plurality of electrically conductive lines of the electrically conductive line pattern layer. An upper surface of the encapsulation layer is flush with an upper surface of the electrically conductive line pattern layer. The first and second adhesive layer are disposed between the electrically conductive line pattern layer and the heat sink element. A bonding strength between the first adhesive layer and the second adhesive layer is greater than 80 kg/cm.sup.2.

Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.

Structured glass articles include a glass substrate including a glass cladding layer fused to a glass core layer, a cavity formed in the glass substrate, and a shielding layer disposed within the cavity. In some embodiments, a passivation layer is disposed within the cavity such that the shielding layer is between the passivation layer and the glass substrate. A method for forming a glass fan-out includes depositing a shielding layer within a cavity in a glass substrate. The glass substrate includes a glass cladding layer fused to a glass core layer. A silicon chip may be deposited within the cavity. In some embodiments, the method also includes depositing a passivation layer within the cavity such that the shielding layer is between the passivation layer and the glass substrate.

A bonded substrate includes: a silicon nitride ceramic substrate; a copper plate; and a bonding layer bonding the copper plate to the silicon nitride ceramic substrate, wherein the bonding layer has a first interface in contact with the silicon nitride ceramic substrate and a second interface in contact with the copper plate, and contains a nitride and a silicide of an active metal as at least one metal selected from the group consisting of titanium and zirconium, an atomic fraction of nitrogen of the bonding layer is greatest at the first interface and is smallest at the second interface, and a sum of atomic fractions of the active metal and silicon of the bonding layer is smallest at the first interface and is greatest at the second interface.

According to one embodiment, a semiconductor device includes a semiconductor chip having a first electrode on a first surface, a metal plate, and a first conductive bonding sheet that is disposed between the first surface of the semiconductor chip and the metal plate and bonds the first electrode to the metal plate.

Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.

A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

A heat dissipation substrate includes: a metal-ceramic composite board, where the metal-ceramic composite board is a metal layer wrapping a ceramic body; and a metal oxide layer integrated with the metal layer and formed in an area of at least a part on an outer surface of the metal layer; and a soldering area on which the metal oxide layer is not formed and that is used to connect with a copper substrate and bear a chip.

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.