A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.

A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1−(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.

A mold includes a mold base material and a rugged structure located at a main surface of the mold base material. The rugged structure includes a plurality of linearly shaped projected portions for forming wiring, and a circularly shaped projected portion for forming a pad portion, in which a light-shielding layer is provided at a top portion flat surface of the circularly shaped projected portion for forming the pad portion.

A method of forming a chip package portion having a reduced loading effect between various metal lines during a leveling process comprises forming a first layer, a passivation layer over the first layer, a second layer over the passivation layer, and a third layer over the second layer. The method also comprises forming a patterned opening having multiple depths by removing portions of the first layer, the passivation layer, the second layer, and the third layer by way of one or more removal processes that remove portions of the first layer, the passivation layer, the second layer, and the third layer in accordance with one or more patterned photoresist depositions. The method further comprises depositing a material into the patterned opening, and leveling the material deposited into the patterned opening.

A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

Methods for forming electrical circuitries on three-dimensional (3D) structures and devices made using the methods. A method includes additively forming and photocuring a 3D structure. The 3D structure is characterized by one or more three-dimensional flexible interconnects (3FIs), an upper level, a lower level, and a pedestal portion. The pedestal portion includes an undercut. The undercut defines an upper level overhang configured to define a mask region over a portion of the lower level. The method includes forming at least two electrically isolated planes of electronic circuitry by directionally depositing a selected material on the one or more 3FIs, the upper level, and one or more non-masked portions of the lower level.

A package structure including a redistribution circuit structure, a wiring substrate, an insulating encapsulation, a buffer layer, a semiconductor device and a stiffener ring is provided. The redistribution circuit structure includes a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The insulating encapsulation is disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate. The buffer layer is disposed over the second surface of the redistribution circuit structure. The semiconductor device is disposed on the buffer layer, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure. The stiffener ring is adhered with the buffer layer by an adhesive.

A semiconductor device includes a base plate, a substrate, a semiconductor element, a case, and a wiring terminal. The case is disposed on the base plate so as to cover the substrate and the semiconductor element. The wiring terminal is electrically connected to the semiconductor element. The case includes a first case unit and a second case unit that is separate from the first case unit. The wiring terminal includes a first wiring unit and a second wiring unit. The first wiring unit is disposed so as to protrude from an inside to an outside of the case, and is electrically connected to the semiconductor element. The second wiring unit is bent with respect to the first wiring unit and disposed outside the case. The first case unit and the second case unit are disposed so as to sandwich the first wiring unit.

Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.