A package structure is provided. The package structure includes a first package component, a second package component, and a lid structure. The first package component includes a plurality of integrated circuit dies and an underfill formed between the integrated circuit dies. The second package component includes a substrate, and the first package component is mounted on the substrate. The lid structure is disposed on the second package component and around the first package component, and the lid structure covers the integrated circuit dies and exposes the underfill.

An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

A semiconductor device includes: an electrically conductive plate; a semiconductor chip on the electrically conductive plate, the semiconductor chip having a front main electrode on a front surface thereof and a back main electrode on a back surface thereof, the back main electrode being bonded to the electrically conductive plate; and a heat radiating member that is bonded to the front main electrode via a conductive adhesive.

An encapsulation chip manufacturing method includes forming first and second dicing grooves in a surface of a cap wafer and aligning the cap wafer and a device substrate such that the surface of the cap wafer faces a surface of the device substrate. The device substrate includes a device affixed to the surface and a bond pad on the surface and coupled to the device. The cap wafer is bonded to the device substrate and partially diced at the first and second dicing grooves such that the bond pad is exposed. Aligning the cap wafer and the device substrate includes aligning the first and second dicing grooves between the bond pad and a bonding area at which the cap wafer is bonded to the device substrate. A width of the first and second dicing grooves prevents cap wafer dust formed during the partial dicing from falling on the bond pad.

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate, and forming a first adhesive element over the substrate. The first adhesive element has a first electrical resistivity. The method also includes forming a second adhesive element over the substrate. The second adhesive element has a second electrical resistivity, and the second electrical resistivity is greater than the first electrical resistivity. The method further includes attaching a protective lid to the substrate through the first adhesive element and the second adhesive element. The protective lid surrounds the chip structure and covers a top surface of the chip structure.

The invention relates to a functional chip (100) of which at least two electrical connection pads (11a, 11b) are intended for being connected to wire elements (40a, 40b). Said chip comprises: —a substrate (10) comprising a microelectronic component electrically connected to the two electrical connection pads arranged on a front face of said substrate (10), —a cover (20) comprising a first portion (21) assembled to the front face of the substrate (10), said first portion (21) forming a spacer between the two electrical connection pads; the cover (20) further comprising a second portion (22) spaced apart from the front face of the substrate (10) and extending opposite each electrical connection pad only partially, so as to allow access to said pads, along an axis (z) normal to the front face of the substrate (10). The invention likewise relates to a method for manufacturing such a functional chip.

In an embodiment A package includes a casing having an opening and enclosing a cavity, a die accommodated in the cavity and a membrane attached to the casing, the membrane being air-permeable, covering and sealing the opening, wherein the membrane is configured to allow only a lateral gas flow, and wherein a blocking member is configured to block a vertical gas flow through the membrane into the cavity, the blocking member tightly covering a surface of the membrane at least in an area comprising the opening.