A light emitting device includes: a base body including two conductive members, a resin body, and a fiber member placed inside the resin body, and a light-emitting element. The resin body includes an isolation section located between the two conductive members, and includes a pair of sandwiching portions sandwiching the isolation section. The fiber member has a length which is greater than a distance between the two conductive members, and is located at least in an adjoining region of at least one of the pair of sandwiching portions, the adjoining region adjoining the isolation section. In the adjoining region, the fiber member extends in a direction which is non-orthogonal to a direction in which that the pair of sandwiching portions extend.

A semiconductor device includes: a conductive portion; and a semiconductor element mounted on the conductive portion, wherein the conductive portion is made of a plating layer, wherein the conductive portion includes a mounting portion having a mounting surface on which the semiconductor element is mounted, and a terminal portion extending to an opposite side of the semiconductor element with respect to the mounting portion, wherein the mounting portion extends in a first direction along the mounting surface more than the terminal portion, and wherein the mounting portion and the terminal portion are integrally formed.

A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.

A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

A processing method of a wafer includes a modified layer forming step of positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the wafer to the inside of a planned dividing line and executing irradiation along the planned dividing line to form modified layers inside and a water-soluble resin coating step of coating the front surface of the wafer with a water-soluble resin before or after the modified layer forming step. The processing method also includes a dividing step of expanding a dicing tape to divide the wafer into individual device chips together with the water-soluble resin with which the front surface of the wafer is coated and a modified layer removal step of executing plasma etching and removing the modified layers that remain at the side surfaces of the device chips in a state in which the dicing tape is expanded and the front surfaces of the individual device chips are coated with the water-soluble resin.

A packaged electronic device includes a multilayer lead frame having first and second trace levels, a via level therebetween, a conductive feed structure, and a conductive reflector wall. The first trace level includes a conductive coupler antenna and a conductive ground structure that extends in a plane of orthogonal first and second directions, and a portion of the conductive coupler antenna faces outward along a third direction orthogonal to the first and second directions. The conductive reflector wall has an opening and extends along the third direction between the first and second trace levels around a portion of the conductive coupler antenna. The conductive feed structure is coupled to the conductive coupler antenna and extends along the first direction through the opening of the conductive reflector wall.

One example described herein includes an integrated circuit (IC) package. The IC package includes a semiconductor die comprising an IC and an IC package enclosure that substantially encloses the semiconductor die. The IC package also includes at least one conductive metal contact. Each of the at least one conductive metal contact is coupled to the semiconductor die and comprises a planar solder surface exterior to the IC package enclosure to which the respective at least one metal contact is soldered to an external conductive metal contact. The planar solder surface includes at least one solder surface feature.

In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.

One example described herein includes a method for fabricating integrated circuit (IC) packages. The method includes fabricating a plurality of IC dies and providing a conductive metal material sheet. The method also includes laser-cutting the conductive metal material sheet to form a lead-frame sheet. The lead-frame sheet includes at least one of through-holes and three-dimensional locking features. The method further includes coupling the IC dies to the lead-frame sheet and coupling the lead-frame sheet and the IC dies to packaging material to form an IC package block comprising the IC packages.