In a frame member including a first region and a second region that are extending in a first direction in parallel to each other while being spaced apart from each other, first and second plating films are formed in the first and second regions, respectively. The second plating film is different in a type from the first plating film. Then, a stamping process is performed to the frame member including the first region and the second region, thereby a lead frame including a plurality of leads is formed. The lead frame includes a first lead group and a second lead group. The first plating film is formed in the first lead group, but the second plating film is not formed in the first lead group. Meanwhile, the second plating film is formed in the second lead group, but the first plating film is not formed in the second lead group.

Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.

In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.

A flexible circuit board and an electronic device including a flexible circuit board are provided. The flexible circuit board may include a substrate having a bending area and a non-bending area, a wiring pattern layer provided on the bending area and the non-bending area, a plating layer provided on the wiring pattern layer and including an open area in an area corresponding to the bending area, and a protective layer that directly contacts one surface of the wiring pattern layer exposed at the open area and a side surface of the plating layer. The protective layer may have a larger thickness than a thickness of the plating layer.

Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.

A method of frame handling during semiconductor package production includes: providing a lead frame having leads secured to a periphery of the lead frame by first tie bars; providing a multi-gauge spacer frame having spacers secured to a periphery of the spacer frame by second tie bars, the spacers being thicker than the second tie bars; and aligning the multi-gauge spacer frame with the lead frame such that the spacers and the second tie bars of the multi-gauge spacer frame do not contact the leads of the lead frame. A power semiconductor module and a method of assembling a power semiconductor module are also described.

A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.

A flexible circuit board includes a substrate a, a wiring pattern layer provided on the first surface of the substrate, a plating layer provided on the wiring pattern layer and including an open area, and a protective layer that contacts parts of the wiring pattern layer, the plating layer, and the substrate. The protective layer has a larger thickness than a thickness of the plating layer. The first protective layer includes a first overlapping region in which the plating layer and protective layer are in contact with each and a second overlapping region in which the plating layer and the protective layer are in contact with each other. A width of the first overlapping region may be different from a width of the second overlapping region, and each of the widths of the first and second overlapping regions is larger than a thickness of the plating layer.

A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.

A semiconductor device is provided, including four flat surfaces on four sides, and two sides include a full lead end height with electroless plating, and the other two sides comprise un-plated exposed Cu tie bar. The full lead end height with electroless plating is an ENIG plating or an ENEPIG plating.