SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

A semiconductor device is provided, including four flat surfaces on four sides, and two sides include a full lead end height with electroless plating, and the other two sides comprise un-plated exposed Cu tie bar. The full lead end height with electroless plating is an ENIG plating or an ENEPIG plating.

Claims

1. A semiconductor device comprising four flat surfaces on four sides; wherein the four sides have two sides that comprise a full lead end height with electroless plating; and wherein the four sides have another two sides that comprise un-plated exposed Cu tie bar.

2. The semiconductor device as claimed in claim 1, wherein semiconductor device comprises side wettable flanks (SWFs).

3. The semiconductor device as claimed in claim 1, wherein the full lead end height with electroless plating is an electroless nickel immersion gold (ENIG) plating or an electroless nickel electroless palladium immersion gold (ENEPIG) plating.

4. The semiconductor device as claimed in claim 2, wherein the full lead end height with electroless plating is an electroless nickel immersion gold (ENIG) plating or an electroless nickel electroless palladium immersion gold (ENEPIG) plating.

5. A method of producing a semiconductor device, the method comprising steps: providing a Cu and Ag spot lead frame; attaching or bonding a die; providing wire bonding; providing a mold or an encapsulation; chopper cut to singulate the molded strips from one side; providing an electroless nickel immersion gold (ENIG) plating or an electroless nickel electroless palladium immersion gold (ENEPIG) plating; and providing a full cut to fully singulate the strips after plating.

6. The method of producing a semiconductor device as claimed in claim 5, wherein the mold is an encapsulation molding compound (EMC).

7. The method of producing a semiconductor device as claimed in claim 5, wherein the target thickness of the ENIG or the ENEPIG plating is: Ni around 2 um, Pd around 0.3 um, and Au around 0.05 um.

8. The method of producing a semiconductor device as claimed in claim 5, wherein the step of the full cut is executed with a thinner blade, to provide a side wettable flank (SWF) at four sides of the semiconductor device with a step.

9. The method of producing a semiconductor device as claimed in claim 5, wherein the step of providing an electroless ENIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; gold immersion; and providing a post treatment.

10. The method of producing a semiconductor device as claimed in claim 5, wherein the step of providing an electroless ENEPIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; providing an electroless palladium plating; gold immersion; and providing a post treatment.

11. The method of producing a semiconductor device as claimed in claim 6, wherein the target thickness of the ENIG or the ENEPIG plating is: Ni around 2 um, Pd around 0.3 um, and Au around 0.05 um.

12. The method of producing a semiconductor device as claimed in claim 6, wherein the step of the full cut is executed with a thinner blade, to provide a side wettable flank (SWF) at four sides of the semiconductor device with a step.

13. The method of producing a semiconductor device as claimed in claim 6, wherein the step of providing an electroless ENIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; gold immersion; and providing a post treatment.

14. The method of producing a semiconductor device as claimed in claim 6, wherein the step of providing an electroless ENEPIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; providing an electroless palladium plating; gold immersion; and providing a post treatment.

15. The method of producing a semiconductor device as claimed in claim 7, wherein the step of the full cut is executed with a thinner blade, to provide a side wettable flank (SWF) at four sides of the semiconductor device with a step.

16. The method of producing a semiconductor device as claimed in claim 7, wherein the step of providing an electroless ENIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; gold immersion; and providing a post treatment.

17. The method of producing a semiconductor device as claimed in claim 7, wherein the step of providing an electroless ENEPIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; providing an electroless palladium plating; gold immersion; and providing a post treatment.

18. The method of producing a semiconductor device as claimed in claim 8, wherein the step of providing an electroless ENIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; gold immersion; and providing a post treatment.

19. The method of producing a semiconductor device as claimed in claim 8, wherein the step of providing an electroless ENEPIG plating, comprising the steps of: electro cleaning; providing an activator; providing an electroless nickel plating; providing an electroless palladium plating; gold immersion; and providing a post treatment.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:

[0043] FIG. 1 shows a known singulation method for an array of leadless packages.

[0044] FIG. 2 illustrates a semiconductor device according to an embodiment of the disclosure.

[0045] FIG. 3 illustrates a method of manufacturing a semiconductor device according to an embodiment of the disclosure.

[0046] FIG. 4 illustrates a method of manufacturing a semiconductor device according to an embodiment of the disclosure, details of step of providing an electroless ENIG or ENEPIG plating.

[0047] FIG. 5 illustrates a method of manufacturing a semiconductor device according to an embodiment of the disclosure.

[0048] FIG. 6 illustrates a method of manufacturing a semiconductor device according to an embodiment of the disclosure.

DETAILED DESCRIPTION

[0049] According to an embodiment of the present disclosure, a side wettable flank (SWF) is created on multiple I/O, more than 6 pins, leadless packages. The SWF can be created through a chopper cut and an electroless plating with electroless nickel immersion gold (ENIG) or electroless nickel electroless palladium immersion gold (ENEPIG). In this way it is enabled to have a SWF on leadless package for thin lead frames, e.g. 100 um lead frames, with full wettable lead end height and flat package surface for four sides. The same plating finishing can be used for a lead-side and a lead-bottom, which is especially important for the high end requirements in automotive industry.

[0050] An embodiment of the present disclosure is shown in FIG. 2. A semiconductor device package 100 comprises six SWF 106, four flat surfaces on four sides, full lead end height with electroless, e.g. ENIG or ENEPIG, plating 104 on two sides and un-plated exposed Cu tie bar 102 on another two sides. Such a semiconductor package 100 can be used for more than six I/O since there is no limitations on the lead frame trace connections.

[0051] According to an embodiment of the present disclosure, as shown in FIG. 3, a method of manufacturing a semiconductor package with SWF with ENIG or ENEPIG plating, comprises the steps: [0052] providing a Cu and Ag spot lead frame, attach/bond a die, provide wire bonding; [0053] providing a mold or an encapsulation; the mold can be encapsulation molding compound (EMC); [0054] chopper cut, so to singulate the molded strips from one side; [0055] provide electroless ENIG or ENEPIG plating; the strips are plated with ENIG/ENEPIG, wherein the target thickness can be: Ni 2 um, Pd 0.3 um, Au 0.05 um; [0056] provide a full cut, so to fully singulate the strips after plating.

[0057] According to an embodiment of the present disclosure, as shown in FIG. 4, a step of providing an electroless ENIG or ENEPIG plating, comprises steps: [0058] electro cleaning [0059] providing an activator [0060] providing an electroless nickel plating [0061] providing an electroless palladium plating, wherein this step is required only for ENEPIG [0062] gold immersion [0063] providing a post treatment.

[0064] According to an embodiment of the present disclosure, as shown in in FIG. 5, a method of manufacturing a semiconductor package comprises steps: [0065] reference sign 200 in FIG. 5: [0066] mold encapsulation, wherein a bottom view of a mold body is shown [0067] reference sign 202 in FIG. 5: [0068] a chopper cut, a through cut for a single site only, exposed side lead for plating process [0069] reference sign 204 in FIG. 5: [0070] an electroless ENIG or ENEPIG plating [0071] reference sign 206 in FIG. 5: [0072] final cut.

[0073] According to an embodiment of the present disclosure, as shown in in FIG. 6, a method of manufacturing a semiconductor package comprises steps: [0074] reference sign 220 in FIG. 6: [0075] a chopper cut partially into EMC on all 4 sides [0076] reference sign 222 in FIG. 6: [0077] an electroless ENIG or ENEPIG plating [0078] reference sign 224 in FIG. 6: [0079] final cut with a thinner blade, which provides a SWF at four sides with a step 226 in a package outline.

[0080] A semiconductor package according to above described embodiments, is especially suitable for a DFN package with SWF, with a thin lead frame based package and enabling full compliance to automotive AOI requirement.

[0081] Particular and preferred aspects of the disclosure are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

[0082] The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed disclosure or mitigate against any or all of the problems addressed by the present disclosure. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

[0083] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

[0084] The term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.