A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

The present disclosure provides a power module and a method for manufacturing the power module. The power module includes a chip, a passive element and connection pins. The connection pins are provided on a pin-out surface of the power module, and are electrically connected to at least one of a chip terminal of the chip and the passive element; a projection of the chip on the pin-out surface of the power module does not overlap with a projection of the passive element on the pin-out surface of the power module, and an angle between the terminal-out surface of the chip and the pin-out surface of the power module is greater than 45 and less than 135.

An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

The present disclosure provides a semiconductor IC structure having vertical wire bonding and method of making it. The method includes two steps. First step: providing a semiconductor chip, disposing a first solder joint and a second solder joint separately on its surface, disposing a wire bonding pad at the first solder joint, to connect to an internal functioning device of the semiconductor chip, and disposing a dummy pad at the second solder joint. Second step: bonding a metal wire on the wire bonding pad, cutting the metal wire on the dummy pad, and breaking the metal wire by pulling above the wire bonding pad, to obtain a vertical conductive column connected to the wire bonding pad.

A semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate. A manufacturing method for a semiconductor module is provided, including: providing a semiconductor chip; solder-bonding a metal wiring plate above said semiconductor chip; and applying a sheet-like low elastic sheet having the elastic modulus lower than that of said metal wiring plate to said metal wiring plate.

A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.

An electromagnetic shielding element and, transmission line assembly and electronic structure package using the same are provided. The electromagnetic shielding element is applied to the transmission line assembly and the electronic structure package to shield electromagnetic noise. The electromagnetic shielding element includes a quantum well structure, and the quantum well structure includes at least two barrier layers and at least one carrier confined layer located between the two barrier layers. Each barrier layer has a thickness between 0.1 nm and 500 nm, and the thickness of the carrier confined layer is between 0.1 nm and 500 nm. The electromagnetic shielding element absorbs electromagnetic wave noise to suppress electromagnetic interference.

A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements.

A device can comprise a plurality of layers stacked and bonded on one another, wherein at least one layer of the plurality of layers comprises: a first active region comprising first pin portions positioned in a first planar arrangement; and a second active region comprising second pin portions positioned in a second planar arrangement, wherein the second planar arrangement is different from the first planar arrangement. The device can also comprise a conformable layer adjacent to at least one of the plurality of layers.