H01L21/4885

Semiconductor device and power converter

A semiconductor device includes: at least one power semiconductor element; a sealing resin disposed so as to seal the power semiconductor element; and a plurality of electrical terminals each electrically connected to the power semiconductor element and each including a protrusion protruding from a surface of the sealing resin. The protrusion includes a first part that is provided on a side of the sealing resin in a protrusion direction of the protrusion and of which a cross-section intersecting the protrusion direction has one of a circular shape and an oval shape.

ELECTRONICS PACKAGE INCLUDING INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELD AND METHOD OF MANUFACTURING THEREOF

An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

Semiconductor Vertical Wire Bonding Structure And Method
20200043889 · 2020-02-06 ·

The present disclosure provides a semiconductor IC structure having vertical wire bonding and method of making it. The method includes two steps. First step: providing a semiconductor chip, disposing a first solder joint and a second solder joint separately on its surface, disposing a wire bonding pad at the first solder joint, to connect to an internal functioning device of the semiconductor chip, and disposing a dummy pad at the second solder joint. Second step: bonding a metal wire on the wire bonding pad, cutting the metal wire on the dummy pad, and breaking the metal wire by pulling above the wire bonding pad, to obtain a vertical conductive column connected to the wire bonding pad.

Methods and Apparatus for Package with Interposers

An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

ELBOW CONTACT FOR FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF
20200027820 · 2020-01-23 ·

A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.

Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof

An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

Elbow contact for field-effect transistor and manufacture thereof

A field-effect transistor (FET) and method of manufacture thereof include a gate, a doped semiconductor structure formed on top of the planar source and drain regions, and a sheath of conducting materials flanking the formed doped semiconductor structure, where the sheath is perpendicular to a surface of the planar source and drain regions.

METHOD FOR FABRICATING A ROW OF MOS TRANSISTORS
20200020589 · 2020-01-16 · ·

A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.

Methods and apparatus for package with interposers

An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Variable pin fin construction to facilitate compliant cold plates

A device can comprise a plurality of layers stacked and bonded on one another, wherein at least one layer of the plurality of layers comprises: a first active region comprising first pin portions positioned in a first planar arrangement; and a second active region comprising second pin portions positioned in a second planar arrangement, wherein the second planar arrangement is different from the first planar arrangement. The device can also comprise a conformable layer adjacent to at least one of the plurality of layers.