To provide an epoxy resin composition capable of forming a polished surface with high flatness when polished after curing, and a method for producing an electronic component mounting structure having a polished surface with high flatness, the polished surface obtained by polishing the surface of an encapsulation body. Disclosed are an epoxy resin composition, an electronic component mounting structure including the epoxy resin composition, and a method for producing the electronic component mounting structure, wherein: the epoxy resin composition includes a fused silica possibly containing hollow particles, and a curing agent; on a polished surface obtained by polishing a cured product of the epoxy resin composition, the number of pores having a diameter of more than 5 μm observed within a 25-mm.sup.2 area is one or less, the pores derived from cross sections of the hollow particles; and the polished surface is coated with a coating material.

A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.

A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.

A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.

Provided a semiconductor chip bonding apparatus including a body, a heater disposed on a lower surface of the body, a collet disposed on a lower surface of the heater, and a head disposed on a lower surface of the collet, the head has a rectangular plate shape, a lower surface and side surfaces of the head are exposed, an upper surface of the head is in contact with the lower surface of the collet, an area of the upper surface of the head is smaller than an area of the lower surface of the collet, the head includes a central section including a recess, and an outer surface constituting a part of the side surfaces of the head, and a peripheral section connected to the recess and disposed on each corners of the head, and a thermal conductivity of the peripheral section is different from that of the central section.

Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

A semiconductor device includes a support body including a mount region, a semiconductor chip disposed on the mount region with a predetermined distance therebetween, a bump disposed between the support body and the semiconductor chip, a wall portion disposed between the support body and the semiconductor chip along a part of an outer edge of the semiconductor chip, and an underfill resin layer disposed between the support body and the semiconductor chip. The underfill resin layer covers an outer side surface of the wall portion.

An electronic device includes a substrate, a bump, a chip, and an adhesive layer. The substrate includes a first connection pad. The bump is disposed on the first connection pad. The chip includes a second connection pad. The bump is disposed between the first connection pad and the second connection pad. The adhesive layer is disposed between the substrate and the chip. A dissipation factor of the adhesive layer is less than or equal to 0.01 at a frequency of 10 GHz. A manufacturing method of an electronic device includes the following: providing a substrate, where the substrate includes a first connection pad; applying an adhesive layer on the substrate; patterning the adhesive layer, such that the adhesive layer produces an opening exposing the first connection pad; forming a bump on the first connection pad; and bonding the chip onto the bump through the second connection pad.

A method for underfilling an electronic circuit assembly may include mounting one or more structures to a substrate, mounting one or more spacers to the substrate at one or more positions, respectively, to form one or more passages between the one or more spacers and the one or more structures, dispensing underfill to the one or more passages, and curing the underfill to secure the one or more structures to the substrate. The one or more structures may include one or more dies.