A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.

A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

A method for packaging an integrated circuit chip includes the steps of: a) providing a plurality of dies and a lead frame which includes a plurality of bonding parts each having a die pad, a plurality of leads each having an end region disposed on and connected to the die pad, and a plurality of bumps each disposed on the end region of a respective one of the leads; b) transferring each of the dies to the die pad of a respective one of the bonding parts to permit each of the dies to be flipped on the respective bonding part; and c) hot pressing each of the dies and the die pad of a respective one of the bonding parts to permit each of the dies to be bonded to the bumps of the respective bonding part.

A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.

A power module includes a metal frame having a first and second device attach pads, first and second semiconductor packages each having an encapsulant body, a die pad exposed at a lower surface of the encapsulant body, a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages and partially covers the metal frame. The first semiconductor package is mounted on the metal frame such that the die pad of the first semiconductor package faces and electrically contacts the first device attach pad. The second semiconductor package is mounted on the metal frame such that the die pad of the second semiconductor package faces and electrically contacts the second device attach pad. The plurality of leads from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.

A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

A semiconductor structure includes a fan-out package, a packaging substrate, an solder material portions bonded to the fan-out package and the packaging substrate, an underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the underfill material portion and having a Young's modulus is lower than a Young's modulus of the underfill material portion.