RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same

Abstract

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.

Claims

1. An apparatus comprising: a mold device die comprising a device region, a first mold compound, and an extra layer, wherein: the device region includes a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, which resides underneath the FEOL portion and comprises connecting layers; the FEOL portion comprises an active layer, a contact layer, and isolation sections, wherein a bottom surface of the active layer and bottom surfaces of the isolation sections are in contact with a top surface of the contact layer, the isolation sections surround the active layer, the isolation sections do not reside over the active layer, and the isolation sections extend vertically beyond a top surface of the active layer to define an opening within the isolation sections and over the active layer; the extra layer is in contact with the top surface of the active layer of the FEOL portion and within the opening, wherein the extra layer is formed of silicon germanium or silicon nitride; and the first mold compound directly resides over the extra layer to fill the opening, wherein no silicon crystal exists between the first mold compound and the active layer; and a multilayer redistribution structure formed underneath the BEOL portion of the mold device die, wherein the multilayer redistribution structure comprises a plurality of bump structures on a bottom surface of the multilayer redistribution structure and redistribution interconnections within the multilayer redistribution structure, wherein the plurality of bump structures are electrically coupled to the FEOL portion of the mold device die via the redistribution interconnections and the connecting layers within the BEOL portion.

2. The apparatus of claim 1 wherein a portion of the first mold compound resides over the isolation sections, wherein the first mold compound is formed of thermoplastics or thermoset polymer materials.

3. The apparatus of claim 1 wherein the extra layer is a passivation layer, which is formed of silicon nitride and fully covers the active layer of the FEOL portion.

4. The apparatus of claim 1 wherein the extra layer is an interfacial layer, which is formed of silicon germanium.

5. The apparatus of claim 1 wherein the first mold compound has a thermal conductivity greater than 1 W/m.Math.K.

6. The apparatus of claim 1 wherein the first mold compound has a dielectric constant less than 8.

7. The apparatus of claim 1 wherein the first mold compound has a dielectric constant between 3 and 5.

8. The apparatus of claim 1 wherein the FEOL portion is configured to provide at least one of a switch field-effect transistor (FET), a diode, a capacitor, a resistor, and an inductor.

9. The apparatus of claim 1 wherein the isolation sections consist of silicon dioxide.

10. An apparatus comprising: a mold device die comprising a device region, a first mold compound, and an extra layer, wherein: the device region includes a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, which resides underneath the FEOL portion and comprises connecting layers; the FEOL portion comprises an active layer, a contact layer, and isolation sections, wherein a bottom surface of the active layer and bottom surfaces of the isolation sections are in contact with a top surface of the contact layer, the isolation sections surround the active layer, the isolation sections do not reside over the active layer, and the isolation sections extend vertically beyond a top surface of the active layer to define an opening within the isolation sections and over the active layer; the extra layer is in contact with the top surface of the active layer of the FEOL portion and within the opening, wherein the extra layer is formed of silicon germanium or silicon nitride; and the first mold compound directly resides over the extra layer to fill the opening, wherein no silicon crystal exists between the first mold compound and the active layer; a multilayer redistribution structure formed underneath the BEOL portion of the mold device die, wherein the multilayer redistribution structure comprises a plurality of bump structures on a bottom surface of the multilayer redistribution structure and redistribution interconnections within the multilayer redistribution structure, wherein the plurality of bump structures are electrically coupled to the FEOL portion of the mold device die via the redistribution interconnections and the connecting layers within the BEOL portion; and a second mold compound residing over the multilayer redistribution structure and encapsulating the mold device die.

11. The apparatus of claim 10 wherein the first mold compound is formed from a same material as the second mold compound.

12. The apparatus of claim 10 wherein the first mold compound and the second mold compound are formed from different materials.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 shows an exemplary radio frequency (RF) device with enhanced thermal and electrical performance according to one embodiment of the present disclosure.

(3) FIG. 2 shows an alternative RF device with enhanced thermal and electrical performance according to one embodiment of the present disclosure.

(4) FIGS. 3-14 provide an exemplary wafer-level packaging process that illustrates steps to fabricate the exemplary RF device shown in FIG. 1.

(5) FIGS. 15-20 provide an alternative wafer-level packaging process that illustrates steps to fabricate the alternative RF device shown in FIG. 2.

(6) It will be understood that for clear illustrations, FIGS. 1-20 may not be drawn to scale.

DETAILED DESCRIPTION

(7) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(8) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(9) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(10) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(11) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(12) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(13) With the looming shortage of conventional radio frequency silicon on insulator (RFSOI) wafers expected in the coming years, alternative technologies are being devised to get around the need for high resistivity using silicon wafers, the trap rich layer formation, and Smart-Cut SOI wafer process. One alternative technology is based on the use of a silicon germanium (SiGe) interfacial layer instead of a buried oxide layer (BOX) between a silicon substrate and a silicon epitaxial layer; however, this technology will also suffer from the deleterious distortion effects due to the silicon substrate, similar to what is observed in an RFSOI technology. The present disclosure, which relates to a radio frequency (RF) device with enhanced thermal and electrical performance, and a wafer-level packaging process for making the same, is based on this Si—SiGe—Si structure without deleterious distortion effects from the silicon substrate.

(14) FIG. 1 shows an exemplary RF device 10 formed from a Si—SiGe—Si wafer (processing details are described in following paragraphs) according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary RF device 10 includes a mold device die 12 with a device region 14 and a first mold compound 16, and a multilayer redistribution structure 18 formed under the mold device die 12.

(15) In detail, the device region 14 includes a front-end-of-line (FEOL) portion 20 and a back-end-of-line (BEOL) portion 22 underneath the FEOL portion 20. In one embodiment, the FEOL portion 20 is configured to provide a switch field-effect transistor (FET), and includes an active layer 24 and a contact layer 26. Herein, the active layer 24 has a source 28, a drain 30, and a channel 32 between the source 28 and the drain 30. The source 28, the drain 30, and the channel 32 are formed from a same silicon epitaxial layer. The contact layer 26 is formed underneath the active layer 24 and includes a gate structure 34, a source contact 36, a drain contact 38, and a gate contact 40. The gate structure 34 may be formed of silicon oxide, and extends horizontally underneath the channel 32 (from underneath the source 28 to underneath the drain 30). The source contact 36 is connected to and under the source 28, the drain contact 38 is connected to and under the drain 30, and the gate contact 40 is connected to and under the gate structure 34. An insulating material 42 may be formed around the source contact 36, the drain contact 38, the gate structure 34, and the gate contact 40 to electrically separate the source 28, the drain 30, and the gate structure 34. In different applications, the FEOL portion 20 may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor.

(16) In addition, the FEOL portion 20 also includes isolation sections 44, which reside over the insulating material 42 of the contact layer 26 and surround the active layer 24. The isolation sections 44 are configured to electrically separate the RF device 10, especially the active layer 24, from other devices formed in a common wafer (not shown). Herein, the isolation sections 44 may extend from a top surface of the contact layer 26 and vertically beyond a top surface of the active layer 24 to define an opening 46 that is within the isolation sections 44 and over the active layer 24. The first mold compound 16 fills the opening 46 and may extend over the isolation sections 44. The isolation sections 44 may be formed of silicon dioxide, which may resist etching chemistries such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH).

(17) In some applications, the RF device 10 may further include a passivation layer 48, which may be formed of silicon dioxide, silicon nitride, or combination of both, directly over the top surface of the active layer 24 and within the opening 46. As such, the first mold compound 16 is directly over the passivation layer 48. The passivation layer 48 is configured to terminate surface bonds of the active layer 24, which may be responsible for unwanted leakage. The passivation layer may also serve as a barrier and is configured to protect the active layer 24 from moisture or ionic contamination. If the passivation layer 48 is omitted, the first mold compound 16 may be in contact with the top surface of the active layer 24. In some applications, the RF device 10 may further include an interfacial layer (described in the following paragraphs and not shown herein), which is formed of SiGe, directly over the top surface of the active layer 24 and within the opening 46. As such, the first mold compound 16 may be directly over the interfacial layer. The interfacial layer is from the Si—SiGe—Si wafer (processing details are described in following paragraphs), which is used to fabricate the RF device 10. If the interfacial layer is omitted, the first mold compound 18 may be in contact with the top surface of the active layer 24. Notice that, regardless of the passivation layer 48 or the interfacial layer, silicon crystal, which has no germanium content, does not exist between the first mold compound 16 and the top surface of the active layer 24. Both the passivation layer 48 and the interfacial layer are silicon alloy.

(18) Further, in some applications, a top surface of each isolation section 44 and the top surface of the active layer 24 are coplanar (not shown), and the opening 46 is omitted. The first mold compound 16 resides over both the active layer 24 and the isolation sections 44 of the FEOL portion 20. Note that the active layer 24 is never vertically beyond the isolation sections 44, otherwise the isolation sections 44 may not fully separate the active layer 24 from other devices formed from the same wafer.

(19) The BEOL portion 22 is underneath the FEOL portion 20 and includes multiple connecting layers 50 formed within dielectric layers 52. Some of the connecting layers 50 are encapsulated by the dielectric layers 52 (not shown), while some of the connecting layers 50 have a bottom portion not covered by the dielectric layers 52. Certain connecting layers 50 are electrically connected to the FEOL portion 20. For the purpose of this illustration, one of the connecting layers 50 is connected to the source contact 36, and another connecting layer 50 is connected to the drain contact 38.

(20) The multilayer redistribution structure 18, which is formed underneath the BEOL portion 22 of the mold device die 12, includes a number of redistribution interconnections 54, a dielectric pattern 56, and a number of bump structures 58. Herein, each redistribution interconnection 54 is connected to a corresponding connecting layer 50 within the BEOL portion 22 and extends over a bottom surface of the BEOL portion 22. The connections between the redistribution interconnections 54 and the connecting layers 50 are solder-free. The dielectric pattern 56 is formed around and underneath each redistribution interconnection 54. A bottom portion of each redistribution interconnection 54 is exposed through the dielectric pattern 56. Each bump structure 58 is formed at a bottom of the multilayer redistribution structure 18 and electrically coupled to a corresponding redistribution interconnection 54 through the dielectric pattern 56. Consequently, the redistribution interconnections 54 are configured to connect the bump structures 58 to certain ones of the connecting layer 50 in the BEOL portion 22, which are electrically connected to the FEOL portion 20. As such, the bump structures 58 are electrically connected to the FEOL portion 20 via corresponding redistribution interconnections 54 and corresponding connecting layers 50. In addition, the bump structures 58 are separate from each other and extend underneath the dielectric pattern 56.

(21) In some applications, some of the redistribution interconnections 54 may be configured to connect the mold device die 12 to other device components formed from the same wafer (not shown). In some applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnections 54 through the dielectric pattern 56, and extra dielectric patterns (not shown) formed underneath the dielectric pattern 56, such that a bottom portion of each extra redistribution interconnection is exposed. Consequently, each bump structure 58 is coupled to a corresponding extra redistribution interconnection through the extra dielectric pattern (not shown). Regardless of the level numbers of the redistribution interconnections and/or the dielectric pattern, the multilayer redistribution structure 18 may be free of glass fiber or glass-free. Herein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections 54 may be formed of copper or other suitable metals. The dielectric pattern 56 may be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The bump structures 58 may be solder balls or copper pillars. The multilayer redistribution structure 18 has a thickness between 2 μm and 300 μm.

(22) The heat generated in the device region 14 may travel upward to a bottom portion of the first mold compound 16, which is over the active layer 24, and then will pass downward through the device region 14 and toward the multilayer redistribution structure 18, which will dissipate the heat. It is therefore highly desirable to have high thermal conductivities of the first mold compound 16. The first mold compound 16 may have a thermal conductivity greater than 1 W/m.Math.K, or greater than 10 W/m.Math.K. In addition, the first mold compound 16 may have a low dielectric constant less than 8, or between 3 and 5 to yield low RF coupling. In one embodiment, the first mold compound 16 may be formed of thermoplastics or thermoset polymer materials, such as PPS (poly phenyl sulfide), overmold epoxies doped with boron nitride, alumina, carbon nanotubes, or diamond-like thermal additives, or the like. A thickness of the first mold compound 16 is based on the required thermal performance of the RF device 10, the device layout, the distance from the multilayer redistribution structure 18, as well as the specifics of the package and assembly. The first mold compound 16 may have a thickness between 200 μm and 500 μm.

(23) FIG. 2 shows an alternative RF device 10A, which further includes a second mold compound 60 compared to the RF device 10. Herein, the multilayer redistribution structure 18 extends horizontally beyond the mold device die 12, and the second mold compound 60 resides over the multilayer redistribution structure 18 to encapsulate the mold device die 12. In this embodiment, the redistribution interconnections 54 of the multilayer redistribution structure 18 may extend horizontally beyond the mold device die 12, and the bump structures 58 of the multilayer redistribution structure 18 may not be confined within a periphery of the mold device die 12. The second mold compound 60 may be formed of a same or different material as the first mold compound 16. Unlike the first mold compound 16, the second mold compound 60 may not have thermal conductivity or dielectric constant requirements.

(24) FIGS. 3-14 provide an exemplary wafer-level packaging process that illustrates steps to fabricate the exemplary RF device 10 shown in FIG. 1. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 3-14.

(25) Initially, a Si—SiGe—Si wafer 62 is provided as illustrated in FIG. 3. The Si—SiGe—Si wafer 62 includes a common silicon epitaxial layer 64, a common interfacial layer 66 over the common silicon epitaxial layer 64, and a silicon handle substrate 68 over the common interfacial layer 66. Herein, the common interfacial layer 66, which is formed of SiGe, separates the common silicon epitaxial layer 64 from the silicon handle substrate 68.

(26) Herein, the common silicon epitaxial layer 64 is formed from a device grade silicon material, which has desired silicon epitaxy characteristics to form electronic devices. The common interfacial layer 66 is formed from an alloy with any molar ratio of Si and Ge. The higher the Ge concentration, the better the etch selectivity between the silicon handle substrate 68 and the common interfacial layer 66, but also the more difficult the epitaxial growth of the common silicon epitaxial layer 64 becomes. In one embodiment, the common interfacial layer 66 may have a Ge concentration greater than 15% or greater than 25%. The Ge concentration may be uniform throughout the common interfacial layer 66. In some applications, the Ge concentration may be vertically graded (between 1% and 50%) so as to yield the necessary strain relief for the growth of the common silicon epitaxial layer 64. The silicon handle substrate 68 may consist of conventional low cost, low resistivity, and high dielectric constant silicon. The common silicon epitaxial layer 64 has higher resistivity, lower harmonic generation, and lower dielectric constant than the silicon handle substrate 68. A thickness of the common silicon epitaxial layer 64 may be between 700 nm and 2000 nm, a thickness of the common interfacial layer 66 may be between 100 nm and 1000 nm, and a thickness of the silicon handle substrate 68 may be between 200 μm and 500 μm.

(27) Next, a complementary metal-oxide-semiconductor (CMOS) process is performed on the Si—SiGe—Si wafer 62 to provide a precursor wafer 70 with a number of device regions 14, as illustrated in FIG. 4A. For the purpose of this illustration, the FEOL portion 20 of each device region 14 is configured to provide a switch FET. In different applications, the FEOL portion 20 may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor.

(28) In this embodiment, the isolation sections 44 of each device region 14 extend through the common silicon epitaxial layer 64 and the common interfacial layer 66, and extend into the silicon handle substrate 68. As such, the common interfacial layer 66 separates into a number of individual interfacial layers 66I, and the common silicon epitaxial layer 64 separates into a number of individual silicon epitaxial layers 641, each of which is used to form a corresponding active layer 24 in one device region 14. The isolation sections 44 may be formed by shallow trench isolation (STI).

(29) The top surface of the active layer 24 is in contact with a corresponding interfacial layer 66I. The silicon handle substrate 68 resides over each individual interfacial layer 66I, and portions of the silicon handle substrate 68 may reside over the isolation sections 44. The BEOL portion 22 of the device region 14, which includes at least the multiple connecting layers 50 and the dielectric layers 52, is formed under the contact layer 26 of the FEOL portion 20. Bottom portions of certain connecting layers 50 are exposed through the dielectric layers 52 at the bottom surface of the BEOL portion 22.

(30) In another embodiment, the isolation sections 44 do not extend into the silicon handle substrate 68. Instead, the isolation sections 44 only extend through the common silicon epitaxial layer 64 and extend into the common interfacial layer 66, as illustrated in FIG. 4B. Herein, the common interfacial layer 66 remains continuous, and the individual interfacial layers 66I are connected with each other. The common interfacial layer 66 directly resides over the top surface of each active layer 24, and directly resides over a top surface of each isolation section 44. The silicon handle substrate 68 remains over the common interfacial layer 66. Further, the isolation sections 44 may extend through the common silicon epitaxial layer 64 but do not extend into the common interfacial layer 66 (not shown). The top surface of each isolation section 44 and the top surface of each active layer 24 may be coplanar (not shown). The common interfacial layer 66 and the silicon handle substrate 68 remain intact. The common interfacial layer 66 is over each isolation section 44 and each active layer 24, and the silicon handle substrate 68 is over the common interfacial layer 66.

(31) After the precursor wafer 70 is completed, the precursor wafer 70 is then bonded to a temporary carrier 72, as illustrated in FIG. 5. The precursor wafer 70 may be bonded to the temporary carrier 72 via a bonding layer 74, which provides a planarized surface to the temporary carrier 72. The temporary carrier 72 may be a thick silicon wafer from a cost and thermal expansion point of view, but may also be construed of glass, sapphire, or other suitable carrier material. The bonding layer 74 may be a span-on polymeric adhesive film, such as the Brewer Science WaferBOND line of temporary adhesive materials.

(32) The silicon handle substrate 68 is then selectively removed to provide an etched wafer 76, wherein the selective removal is stopped on each interfacial layer 66I, as illustrated in FIG. 6. If the isolation sections 44 extend vertically beyond the interfacial layers 66I, the removal of the silicon handle substrate 68 will provide the opening 46 over each active layer 24 and within the isolation sections 44. Removing the silicon handle substrate 68 may be provided by chemical mechanical grinding and an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, NaOH, ACH, or XeF2, or provided by the etching process itself. As an example, the silicon handle substrate 68 may be ground to a thinner thickness to reduce the following etching time. An etching process is then performed to completely remove the remaining silicon handle substrate 68. Since the silicon handle substrate 68 and the interfacial layers 66I have different characteristics, they may have different reactions to a same etching technique (for instance: different etching speeds with a same etchant). Consequently, the etching system is capable of identifying the presence of the interfacial layers 66I, and capable of indicating when to stop the etching process.

(33) During the removal process, the isolation sections 44 are not removed and protect sides of each FEOL portion 20. The bonding layer 74 and the temporary carrier 72 protect the bottom surface of each BEOL portion 22. Herein, the top surface of each isolation section 44 and the top surface of each interfacial layer 66I are exposed after the removing process. If the isolation sections 44 only extend into the common interfacial layer 66 but not through the common interfacial layer 66 (as shown in FIG. 3B), or the top surface of each isolation section 44 and the top surface of each active layer 24 are coplanar (not shown), only the top surface of the common interfacial layer 66 is exposed (not shown).

(34) Due to the narrow gap nature of the SiGe material, it is possible that the interfacial layers 66I (or the common interfacial layer 66) may be conducting. The interfacial layer 66I may cause appreciable leakage between the source 28 and the drain 30 of the active layer 24. Therefore, in some applications, such as FET applications, it is desired to also remove the interfacial layers 66I (or the common interfacial layer 66), as illustrated in FIG. 7. The interfacial layers 66I may be removed by the same etching process used to remove the silicon handle substrate 68, or may be removed by another etching process, such as HCI dry etch systems. If the interfacial layer 66I is thin enough, it may be completely depleted and may not cause any appreciable leakage between the source 28 and the drain 30 of the FEOL portion 20. In that case, the interfacial layers 66I may be left intact.

(35) In some applications, the passivation layer 48, which may be formed of silicon dioxide, silicon nitride, or combination of both, may be formed directly over the active layer 24 of each FEOL portion 20, as illustrated in FIG. 8. If there is the opening 46 over each active layer 24 and within the isolation sections 44, the passivation layer 48 is formed within the opening 46. The passivation layer 48 is configured to terminate the surface bonds at the top surface of the active layer 24, which may be responsible for unwanted leakage. The passivation layer 48 may be formed by CVD dielectric filming or passivating plasma.

(36) Next, the first mold compound 16 is applied over the etched wafer 76 to provide a mold device wafer 78, as illustrated in FIG. 9. The mold device wafer 78 includes a number of the mold device dies 12, each of which includes the device region 14, and a portion of the first mold compound 16. Herein, the first mold compound 16 fills each opening 46 and is in contact with the passivation layer 48 within the opening 46. In addition, portions of the first mold compound 16 may extend over the isolation sections 44. If there is no passivation layer 48 formed in each opening 46, the first mold compound 16 is in contact with the top surface of each active layer 24 (not shown). If the interfacial layer 66I remains over the top surface of each active layer 24, the first mold compound 16 is in contact with the interfacial layer 66I (not shown). The first mold compound 16 always resides over each active layer 24.

(37) The first mold compound 16 may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. The first mold compound 16 may have a superior thermal conductivity greater than 1 W/m.Math.K, or greater than 10 W/m.Math.K, and may have a dielectric constant less than 8, or between 3 and 5. During the molding process of the first mold compound 16, the temporary carrier 72 provides mechanical strength and rigidity to the etched wafer 76. A curing process (not shown) is followed to harden the first mold compound 16. The curing temperature is between 100° C. and 320° C. depending on which material is used as the first mold compound 16. After the curing process, the first mold compound 16 may be thinned and/or planarized (not shown).

(38) The temporary carrier 72 is then debonded from the mold device wafer 78, and the bonding layer 74 is cleaned from the mold device wafer 78, as illustrated in FIG. 10. A number of debonding processes and cleaning processes may be applied depending on the nature of the temporary carrier 72 and the bonding layer 74 chosen in the earlier steps. For instance, the temporary carrier 72 may be mechanically debonded using a lateral blade process with the stack heated to a proper temperature. Other suitable processes involve radiation of UV light through the temporary carrier 72 if it is formed of a transparent material, or chemical debonding using a proper solvent. The bonding layer 74 may be eliminated by wet or dry etching processes, such as proprietary solvents and plasma washing. After the debonding and cleaning process, the bottom portions of certain ones of the connecting layers 50, which may be functioned as input/output (I/O) ports of the mold device die 12, are exposed through the dielectric layers 52 at the bottom surface of each BEOL portion 22. As such, each mold device die 12 in the mold device wafer 78 may be electrically verified to be working properly at this point.

(39) With reference to FIGS. 11 through 13, the multilayer redistribution structure 18 is formed underneath the mold device wafer 78 according to one embodiment of the present disclosure. Although the redistribution steps are illustrated in a series, the redistribution steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, redistribution steps within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 11-13.

(40) A number of the redistribution interconnections 54 are firstly formed underneath each BEOL portion 22, as illustrated in FIG. 11. Each redistribution interconnection 54 is electrically coupled to the exposed bottom portion of the corresponding connecting layer 50 within the BEOL portion 22, and may extend over the bottom surface of the BEOL portion 22. The connections between the redistribution interconnections 54 and the connecting layers 50 are solder-free. The dielectric pattern 56 is then formed underneath each BEOL portion 22 to partially encapsulate each redistribution interconnection 54, as illustrated in FIG. 12. As such, the bottom portion of each redistribution interconnection 54 is exposed through the dielectric pattern 56. In different applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnection 54 through the dielectric pattern 56, and extra dielectric patterns (not shown) formed underneath the dielectric pattern 56, such that a bottom portion of each extra redistribution interconnection is exposed.

(41) Next, a number of the bump structure 58 are formed to complete the multilayer redistribution structure 18 and provide a wafer-level fan-out (WLFO) package 80, as illustrated in FIG. 13. Each bump structure 58 is formed at the bottom of the multilayer redistribution structure 18 and electrically coupled to an exposed bottom portion of the corresponding redistribution interconnection 54 through the dielectric pattern 56. Consequently, the redistribution interconnections 54 are configured to connect the bump structures 58 to certain ones of the connecting layer 50 in the BEOL portion 22, which are electrically connected to the FEOL portion 20. As such, the bump structures 58 are electrically connected to the FEOL portion 20 via corresponding redistribution interconnections 54 and corresponding connecting layers 50. In addition, the bump structures 58 are separate from each other and extend underneath the dielectric pattern 56.

(42) The multilayer redistribution structure 18 may be free of glass fiber or glass-free. Herein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections 54 may be formed of copper or other suitable metals, the dielectric pattern 56 may be formed of BCB, polyimide, or other dielectric materials, and the bump structures 58 may be solder balls or copper pillars. The multilayer redistribution structure 18 has a thickness between 2 μm and 300 μm. FIG. 14 shows a final step to singulate the WLFO package 80 into individual RF devices 10. The singulating step may be provided by a probing and dicing process at certain isolation sections 44.

(43) In another embodiment, FIGS. 15-20 provide an alternative wafer-level packaging process that illustrates steps to fabricate the alternative RF device 10A shown in FIG. 2. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 15-20.

(44) After the debonding and cleaning process to provide the clean mold device wafer 78 as shown in FIG. 10, a singulating step is followed to singulate the mold device wafer 78 into individual mold device dies 12, as illustrated in FIG. 15. Each mold device die 12 may have a same height and includes the device region 14 with the FEOL portion 20 and the BEOL portion 22 and the first mold compound 16.

(45) Next, the second mold compound 60 is applied around and over the mold device dies 12 to provide a double mold device wafer 82, as illustrated in FIG. 16. The second mold compound 60 encapsulates a top surface and side surfaces of each mold device die 12, while a bottom surface of each mold device die 12, which is the bottom surface of the BEOL portion 22, is exposed. A bottom surface of the double mold device wafer 82 is a combination of the bottom surface of each mold device die 12 and a bottom surface of the second mold compound 60. Herein, the bottom portions of certain ones of the connecting layers 50 remain exposed at the bottom surface of each mold device die 12. The second mold compound 60 may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, or screen print encapsulation. The second mold compound 60 may be formed of the same or different material as the first mold compound 16. However, unlike the first mold compound 16, the second mold compound 60 does not have thermal conductivity or electrical resistivity requirements. The second mold compound 60 may be an organic epoxy resin system or the like. A curing process (not shown) is then used to harden the second mold compound 60. The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound 60. A grinding process (not shown) may be followed to provide a planarized top surface of the second mold compound 60.

(46) With reference to FIGS. 17 through 19, the multilayer redistribution structure 18 is formed according to one embodiment of the present disclosure. Although the redistribution steps are illustrated in a series, the redistribution steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, redistribution steps within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 17-19.

(47) A number of the redistribution interconnections 54 are firstly formed underneath the double mold device wafer 82, as illustrated in FIG. 17. Each redistribution interconnection 54 is electrically coupled to the corresponding connecting layer 50 within the BEOL portion 22, and may extend horizontally beyond the corresponding mold device die 12 and underneath the second mold compound 60. The connections between the redistribution interconnections 54 and the connecting layers 50 are solder-free. The dielectric pattern 56 is then formed underneath the double mold device wafer 82 to partially encapsulate each redistribution interconnection 54, as illustrated in FIG. 18. As such, the bottom portion of each redistribution interconnection 54 is exposed through the dielectric pattern 56. In different applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnection 54 through the dielectric pattern 56, and extra dielectric patterns (not shown) formed underneath the dielectric pattern 56, such that a bottom portion of each extra redistribution interconnection is exposed.

(48) Next, a number of the bump structures 58 are formed to complete the multilayer redistribution structure 18 and provide an alternative WLFO package 80A, as illustrated in FIG. 19. Each bump structure 58 is formed at the bottom of the multilayer redistribution structure 18 and electrically coupled to an exposed bottom portion of the corresponding redistribution interconnection 54 through the dielectric pattern 56. Consequently, the redistribution interconnections 54 are configured to connect the bump structures 58 to certain ones of the connecting layer 50 in the BEOL portion 22, which are electrically connected to the FEOL portion 20. As such, the bump structures 58 are electrically connected to the FEOL portion 20 via corresponding redistribution interconnections 54 and corresponding connecting layers 50. Herein, the bump structures 58 may not be confined within a periphery of a corresponding mold device die 12. In addition, the bump structures 58 are separate from each other and extend underneath the dielectric pattern 56.

(49) FIG. 20 shows a final step to singulate the alternative WLFO package 80A into individual alternative RF devices 10A. The singulating step may be provided by a probing and dicing process at portions of the second mold compound 60, which are horizontally between adjacent mold device dies 12.

(50) Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.