The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.

A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.

A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.

Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

The present invention relates to a process of a surface-mounting three-dimensional package structure electrically connected by a pre-packaged metal, comprising: taking a metal sheet; punching or etching the metal sheet; packaging a conductive metal-pillar frame; performing windowing and slotting; taking a substrate on which a chip is surface-mounted; fitting the conductive metal-pillar frame; performing packaging and grinding; surface-mounting a passive device; performing plastic packaging and ball-mounting; and performing cutting. The process of the present invention can improve the integration level and the reliability.

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

A method of manufacturing an implantable stimulation device includes providing a circuit board of the implantable stimulation device, the circuit board optionally equipped with circuit components and being electrically connected to an antenna, adhering one or more electrodes to the circuit board, and applying an insulation material to the circuit board such that the insulation material forms a housing that surrounds the circuit board, the optional circuit components and antenna, while leaving the one or more electrodes exposed for stimulating a tissue.

A memory device includes a substrate, a controller die, a flip chip die, first and second silicon dies, and bond wires. The controller and flip chip dies are attached to the substrate using connection balls and in electrical communication with each other. The first and second silicon dies include respective first and second contact pad surfaces. The bond wires electrically connect the contact pad surfaces to the substrate so the first and second silicon dies communicate with the controller die. The flip chip die and first and second silicon dies are NAND dies, the flip chip die is configured as SLC memory, and the silicon dies are configured as one of MLC memory, TLC memory, or QLC memory.