An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.

A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.

A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.

The invention relates to a thermode for connecting at least two components, comprising a tip having a body portion with at least two contact surface portions connected to and spaced apart from one another by a recess configured to receive a portion of one of the at least two components; and a support portion having at least one supporting surface portion configured to support a further component (being the other of the at least two components, wherein the contact surface portions and the supporting surface portion are configured to receive the at least two components between them and wherein one or both of the contact surface portions and the supporting surface portion are moveable relative to and towards one another to exert heat and/or pressure on the at least two components located between the contact surface portions and the supporting portion.

A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame.

Edge interconnects for interconnecting solar cells are disclosed. The edge interconnects include a layer of an electrically conductive adhesive overlying an insulating dielectric layer applied to edge of a solar cell and electrically interconnected to a busbar. Solar cell modules include adjacent solar cells comprising edge interconnects interconnected using an interconnection element. An interconnection element can be a solder paste or a solder containing electrically conductive ribbon. Methods of forming solar cell edge interconnects include applying an insulating dielectric coating to edges of a solar cell, depositing a busbar in proximity to the insulated edges of the solar cell, depositing an electrically conductive adhesive over at least portion of the busbar an over at least a portion of the dielectric layer. Solar cell modules can be formed by interconnecting adjacent solar cells using an interconnection element.

Provided is a power module package including: a substrate; at least one electrode arranged on the substrate; and an encapsulation member covering at least a portion of the substrate, the encapsulation member including a housing unit housing the at least one electrode. The at least one electrode is spaced apart from the encapsulation member.

A dual side cooling power module includes: a lower substrate including a recessed portion on at least one surface thereof, a semiconductor chip formed in the recessed portion, lead frames formed at both ends of the lower substrate, and an upper substrate formed on the semiconductor chip, a portion of the lead frames, and the lower substrate.

Edge interconnects for interconnecting solar cells are disclosed. The edge interconnects include a layer of an electrically conductive adhesive overlying an insulating dielectric layer applied to edge of a solar cell and electrically interconnected to a busbar. Solar cell modules include adjacent solar cells comprising edge interconnects interconnected using an interconnection element. An interconnection element can be a solder paste or a solder containing electrically conductive ribbon. Methods of forming solar cell edge interconnects include applying an insulating dielectric coating to edges of a solar cell, depositing a busbar in proximity to the insulated edges of the solar cell, depositing an electrically conductive adhesive over at least portion of the busbar an over at least a portion of the dielectric layer. Solar cell modules can be formed by interconnecting adjacent solar cells using an interconnection element.