A method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate lower in rigidity than the first substrate to a first principal surface, on which the first structure is formed, of the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The second substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the second substrate is removed, of the second bonded body. The supporting substrate is removed from the third bonded body.

A method for manufacturing a photoelectric conversion device, that includes: forming a laminate structure of a substrate, a transparent electrode, an active layer produced by wet-coating, and a counter electrode, stacked in this order; and thereafter forming a cavity by: (a) pressing an adhesive material just against a defect formed on the surface of said counter electrode, and then peeling off said adhesive material together with said defect and the peripheral part thereof; or (b) sucking a defect formed on the surface of said counter electrode, so as to remove said defect and the peripheral part thereof, where said cavity penetrates through the counter electrode and unreached to the transparent electrode.

A substrate bonding apparatus includes a first bonding chuck configured to support a first substrate and a second bonding chuck configured to support a second substrate such that the second substrate faces the first substrate. The first bonding chuck includes a first base, a first deformable plate on the first base and configured to support the first substrate and configured to be deformed such that a distance between the first base and the first deformable plate is varied, and a first piezoelectric sheet on the first deformable plate and configured to be deformed in response to power applied thereto to deform the first deformable plate.

Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.

The semiconductor device manufacturing method includes a bonding step of bonding a wire to an electrode (35a), a looping wire formation step of looping the wire from the electrode (35a) to a dummy electrode (34) to form a looping wire (50a), a pressing step of pressing a part of the wire, a moving step of moving the pressed part of the wire directly above the electrode, a wire separation step of separating the wire partially from a wire supply to form a pin wire (55a) extending vertically upward from the electrode (35a), wherein the looping wire formation step adjusts the looping height of the wire to set the length of the looping wire to a predetermined length.

The semiconductor device manufacturing method includes a bonding step of bonding a wire to an electrode (35a), a looping wire formation step of looping the wire from the electrode (35a) to a dummy electrode (34) to form a looping wire (50a), a pressing step of pressing a part of the wire, a moving step of moving the pressed part of the wire directly above the electrode, a wire separation step of separating the wire partially from a wire supply to form a pin wire (55a) extending vertically upward from the electrode (35a), wherein the looping wire formation step adjusts the looping height of the wire to set the length of the looping wire to a predetermined length.

A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.