A method for producing mirror-polished wafer, the method produces a plurality of mirror-polished wafers by performing, on plurality of silicon wafers obtained by slicing a silicon ingot, slicing strain removing step of removing strain on a surface caused by slicing, etching step of removing strain caused by the slicing strain removing step, and double-side polishing step of performing mirror polishing on both surfaces of the silicon wafers subjected to etching, each step being performed by batch processing, wherein silicon wafers which are processed in double-side polishing step by batch processing are selected from silicon wafers processed in same batch in the slicing strain removing step and the number of silicon wafers to be selected is made to be equal to the number of silicon wafers processed in the slicing strain removing step or submultiple thereof. As a result, a method that can produce mirror-polished wafers having high flatness is provided.

This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

A substrate processing apparatus, including: a process chamber configured to process substrates; a substrate mounting stand installed in the process chamber and configured to support the substrates along a circumferential direction; a rotating unit configured to rotate the substrate mounting stand; a first gas supply unit configured to supply a first gas from above the substrate mounting stand; a second gas supply unit configured to supply a second gas from above the substrate mounting stand; a third gas supply unit configured to supply a cleaning gas from above the substrate mounting stand; and an elevating unit configured to maintain the substrate mounting stand at a substrate processing position while supplying the first gas and the second gas and also configured to maintain the substrate mounting stand at a cleaning position while supplying the cleaning gas.

Apparatus and methods of measuring and controlling the gap between a susceptor assembly and a gas distribution assembly are described. Apparatus and methods for positional control and temperature control for wafer transfer purposes are also described.

Provided are a gas injection device and substrate processing apparatus using the same. The gas injection device includes a plurality of gas injection units disposed above a substrate support part rotatably disposed within a chamber to support a plurality of substrates, the plurality of gas injection units being disposed along a circumference direction with respect to a center point of the substrate support part to inject a process gas onto the substrates. Wherein each of the plurality of gas injection units includes a top plate in which an inlet configured to introduce the process gas is provided and an injection plate disposed under the top plate to define a gas diffusion space between the injection plate and the top plate along a radius direction of the substrate support part, the injection plate having a plurality of gas injection holes under the gas diffusion space to inject the process gas introduced through the inlet and diffused in the gas diffusion space onto the substrate. In at least one gas injection unit of the plurality of gas injection units, the process gas is introduced into the gas diffusion space at a plurality of points.

A method and apparatus for polishing a substrate is disclosed herein. More specifically, the apparatus relates to an integrated CMP system for polishing substrates. The CMP system has a polishing station configured to polish substrates. A spin rinse dry (SRD) station configured to clean and dry the substrates. A metrology station configured to measure parameters of the substrates. A robot configured to move the substrate in to and out of the SRD station. And an effector rinse and dry (EERD) station configured to clean and dry an end effector of the robot.

A substrate processing apparatus that performs a film formation process on a substrate placed on one side of a rotary table includes: a main heating mechanism configured to heat the substrate; an auxiliary heating mechanism configured to adjust an intensity of light irradiated from the auxiliary heating mechanism in an inward/outward direction of the rotary table; a temperature measurement part configured to detect a temperature distribution of the substrate in the inward/outward direction of the rotary table; a position detection part configured to detect a position of the rotary table in a rotational direction of the rotary table; and a control part configured to control the intensity of the light irradiated from the auxiliary heating mechanism based on a temperature measurement data obtained by the temperature measurement part, a data corresponding to a target temperature distribution of the substrate, and a position detection value detected by the position detection part.

A heater assembly having a backside purge gap formed between a top plate and a heater of the heater assembly, the top plate having a top plate wall. The top plate wall having an upper portion, a middle portion and a lower portion, the middle portion forming an incline relative to the top portion.

A graphite wafer carrier for LED epitaxial wafer processes, having a plurality of wafer pocket profiles above the carrier for carrying the epitaxial wafer substrate. The inner edge of the wafer pocket profile is a concave step with a plurality of inward-extended support portions; and also has a graphite wafer carrier edge and an axle hole at the center of the graphite wafer carrier. The pocket profiles of different quantities and sizes can be arranged on the basis of different process parameters. The disclosed structure can reduce or eliminate airflow interference and improve the wafer edge yield.