The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+source and a second pwell is on an opposite side of the nwell finger including a p+drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

A semiconductor device is provided. The device comprises: a first transistor that includes a first primary terminal, a second primary terminal and a first control terminal; a second transistor that includes a third primary terminal, a fourth primary terminal and a second control terminal; and a resistive element. The first and third primary terminal are connected to a first voltage line. The second primary terminal and one terminal of the resistive element are connected to a second voltage line. The first and second control terminal, the fourth primary terminal and the other terminal of the resistive element are connected to a node. A potential change in the third primary terminal is transmitted to the first control terminal by capacitive coupling between the third primary terminal and the node, turning on the first transistor.

A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.

An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.

A method for forming a semiconductor device includes incorporating dopants of a first conductivity type into a nearby body region portion of a semiconductor substrate having a base doping of the first conductivity type. The incorporation of the dopants of the first conductivity type is masked by a mask structure at at least part of an edge region of the semiconductor substrate. The method further includes forming a body region of a transistor structure of a second conductivity type in the semiconductor substrate. The nearby body region portion of the semiconductor substrate is located adjacent to the body region of the transistor structure.

Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.