Method for growing III-V epitaxial layers

Abstract

Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.

Claims

1. A method of manufacturing a device comprising a semiconductor structure, wherein the method comprises: providing a substrate; providing an epitaxial semiconducting buffer layer on top of the substrate, thereby obtaining a conductive interface between the buffer layer and the substrate; forming one or more protective layers over the buffer layer, wherein the one or more protective layers comprise one or more layers selected from the group consisting of a III-V layer, a SiN layer, and combinations thereof; and forming one or more local electrical isolations at the conductive interface and partly in the substrate, thereby interrupting electric current at the conductive interface, wherein the one or more local electrical isolations are positioned such that at least one of the one or more local electrical isolations is located between a high voltage terminal and a low voltage terminal of the device.

2. The method of claim 1, wherein the one or more local electrical isolations are formed by at least one of a shallow trench isolation, local oxidation of silicon, impurity implantation, deep trench etching, or combinations thereof.

3. The method of claim 1, wherein the one or more local electrical isolations are formed in a regular pattern.

4. The method of claim 3, wherein: the device comprises a gate and a drain, wherein the gate is separate from the drain by a distance; and a period of the regular pattern is less than the distance, wherein the period and the distance are in the same plane.

5. The method of claim 3, further comprising positioning the pattern such that a gate of the device is located vertically above the pattern.

6. The method of claim 1, wherein the one or more local electrical isolations are positioned between a gate and a drain of the device.

7. The method of claim 1, wherein: the one or more protective layers are formed over the buffer layer before forming the one or more local electrical isolations.

8. The method of claim 1, wherein the one or more protective layers comprise (i) a stack of GaN applied on the buffer layer, (ii) an AlN applied on the GaN layer, and (iii) a SiN layer applied on the AlN layer.

9. The method of claim 1, further comprising removing the one or more protective layers prior to a re-growth.

10. The method of claim 9, wherein the one or more local electrical isolations form a surface, the method further comprising, prior to removing the one or more protective layers, planarizing the surface.

11. The method of claim 9, wherein the re-growth comprises selectively re-growing a III-V layer by patterning at least one of the substrate and the buffer layer with isolation patterns.

12. A device comprising a semiconductor structure being a transistor or a diode, the semiconductor structure comprising: a substrate comprising one or more of the following: Si, SiGe, Ge, Silicon-On-Insulator, or Ge-On-Insulator; a III-V buffer layer on top of the substrate, wherein a conductive interface is formed between the buffer layer and the substrate, and a conductive path is present in the conductive interface; and one or more electrical isolations formed at the conductive interface, wherein the one or more electrical isolations interrupt the conductive path and extend through the III-V buffer layer into the substrate, wherein the one or more local electrical isolations are formed with the device such that: at least one of the one or more local electrical isolations is formed between a gate and a drain of the device; a gate of the device is located vertically above the one or more local electrical isolations; or at least one of the local electrical isolations is formed between a cathode and an anode of the device.

13. The device of claim 12, wherein each of the one or more electrical isolations has a width of between 25 nm and 2.5 μm.

14. The device of claim 12, wherein a space between the one or more electrical isolations is between 0.2 μm and 20 μm wide.

15. The device of claim 12, wherein: the one or more local electrical isolations are formed in a regular pattern; and a period of the regular pattern is smaller than a gate to drain distance, wherein the period and the distance are in the same plane.

16. The device of claim 12, wherein the substrate has been removed locally.

17. The device of claim 12, wherein the device is configured for use in an electronic circuit selected from the group consisting of a switch, a high-power application, a bidirectional power switching application, a high-voltage application, a power conversion circuit, an image sensor, a biosensor, a gas sensor, and an ion sensor.

18. The device of claim 12, wherein the one or more local electrical isolations are formed by at least one of a shallow trench isolation, local oxidation of silicon, impurity implantation, deep trench etching, or combinations thereof.

19. The device of claim 12, wherein: the III-V buffer layer is capped with one or more protective layers before forming the one or more local electrical isolations; and the one or more protective layers comprise one or more layers selected from the group consisting of a III-V layer, a SiN layer, and combinations thereof.

20. The device of claim 19, wherein the one or more protective layers comprise (i) a stack of GaN applied on the buffer layer, (ii) an AlN applied on the GaN layer, and (iii) a SiN layer applied on the AlN layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a cross section of a semiconductor device according to the prior art.

(2) FIG. 2 shows a cross section of a method of manufacturing a semiconductor device according to the invention.

(3) FIGS. 3a-b show cross sections of a method of manufacturing a semiconductor device according to the invention.

(4) FIGS. 4-7 and 8a-d show cross sections of a method of manufacturing a semiconductor device according to the invention.

(5) FIGS. 9a-f show top views of a method of manufacturing a semiconductor device according to the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

(6) The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

(7) It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

(8) Similarly, it is to be noticed that the term “coupled” should not be interpreted as being restricted to direct connections only. Thus, the scope of the expression “a device A coupled to a device B” should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means.

(9) The invention will be described by a detailed description of several embodiments of the invention. It is obvious that other embodiments of the invention can be configured by a person skilled in the art without departing form the true spirit or technical teaching of the invention, the invention therefore being limited only by the terms of the appended claims.

(10) The invention is mainly related to materials (e.g. a wide bandgap on a substrate such as Si) rather than a specific device technology. It is anticipated that the present invention is not particularly limited by the processing technology. Hence it will be clear for a person skilled in the art that the present invention is also applicable to similar circuits that can be configured in any transistor technology, including for example, but not limited thereto, Bipolar, CMOS, BICMOS.

(11) Description of the invention and manufacturing steps.

(12) In an example of the present invention an epitaxial buffer structure (layer 2) on a substrate (layer 1) is provided consisting of an AlN nucleation layer and optionally consisting of one or more (In)AlGaN buffer layers which are capped in-situ with a protective layer stack consisting of GaN (layer 3), optionally Al(Ga)N (layer 4) and SiN (layer 5) (see as comparison FIG. 1, reflecting prior art). The structure further comprises a conductive channel, formed between the substrate and buffer structure layer (indicated with arrows in FIG. 1). This structure may be subjected to various standard semiconductor process steps (such as litho, etching, depositions, implant, oxidation, etc.) and yet can still be re-introduced in the MOCVD reactor for selective epitaxial re-growth onto the buffer layers.

(13) In an example the substrate (1) is Si <111>. In another example, the substrate (1) is Ge <111>. In another example, the substrate (1) is Si with a crystalline Ge cap. There may be SiGe transitional layer between the Si and the Ge.

(14) In an example the AlN nucleation layer is typically 200 nm thick (50 nm-500 nm). AlGaN buffer layers are in an example individually typically 300 nm thick (50 nm-500 nm), with an Al content typically varying between 0%-100%, preferably between 1%-99%, more preferably between 20% and 90%, such as 50%. These buffer layers can also optionally have some other III-element, such as Indium, in them. A total AlGaN buffer (2) is typically 100 nm to 5 μm thick, such as from 500 nm to 4 μm thick. In an example typical thicknesses of the individual layers in the protective layer stack are 0.1 nm-100 nm, such as 5 nm for the GaN, 0 nm-100 nm, such as 2 nm for the Al(Ga)N and 50 nm-500 nm, such as 200 nm for the SiN.

(15) A top protection layer such as a SiN (layer 5) will amongst others protect the underlying III-nitride layers during any process steps necessary (e.g. patterned trench etching, STI formation, deep trench isolation, patterned implantation, etc.) because of its high temperature stability and chemical properties. SiN (together with SiOx) is commonly used dielectrics in Si CMOS technology, in particular as a (sacrificial) capping material to protect sensitive wafer areas during additional processing. In a preferred example, this layer is SiN with high density, deposited in-situ in the MOCVD reactor. This SiN may be stoechiometric or non-stoechiometric. In another example, the SiN may contain some Al (AlSiN). In an example it is typically 50 nm-500 nm, such as 200 nm thick. Upon termination of the process, this SiN will be removed either by a dry or wet etch (in F-based chemistry). The in-situ SiN may be thickened externally by PECVD or LPCVD SiN or SiOx (for thicknesses beyond 500 nm) or any other material or material stack before any other processing takes place.

(16) In a preferred example, interruption of the conductive channel is done by a modified STI process (see FIGS. 2 and 3a and 3b), in which (preferably periodic and repetitive) lithographical patterns define location of trenches (6a). The trenches are etched through the SiN and all III-nitride buffer layers into the Si substrate, e.g. by using a Cl-based dry etching process (see FIG. 2). After removal of a resist, sidewalls of the trench are e.g. thermally oxidised and e.g. CVD SiOx (or SiN or a combination thereof) is deposited in order to fill the trenches (see FIG. 3a). In an example in a last step of the STI process (see FIG. 3b), the wafer is planarized in a chemical mechanical polishing (CMP) step.

(17) In an example typically the trenches are 25 nm-2.5 μm wide, preferably 50 nm-1.5 μm wide, more preferably 100 nm-1 μm wide, such as 200-500 nm wide, and/or wherein a space between the one or more local isolations is 0.2 μm-20 wide, preferably 0.5 μm -10 μm wide, more preferably 1 μm-5 μm wide. In a preferred example, the period of the STI pattern in the longitudinal direction of the device is (significantly) smaller than the gate to drain distance (defined in the same direction), to ensure that at least one continuous trench will be located between gate and drain. Typical examples of patterns can be found in FIGS. 9a through 9f, such as rectangular, triangular, hexagonal, circular and elliptical, square, multigonal, etc. In another example, the STI patterns and the device are designed in such way and positioned or aligned to each other in the device lithography processes. In an example, the positioning or alignment is performed such that at least one, or a single, trench is located between a high voltage (or first) and a low voltage (or second) terminal of the device. In an example, the positioning or alignment is performed such that at least one, or a single, trench is located only in between a high and a low voltage terminal of the device, and not under or below said high or low voltage terminals.

(18) In an example, the positioning or alignment is performed such that the at least one, or the single, i.e. all, trench(es) which is/are located in between a high and a low voltage terminal of the device, are/is located only in between a high and a low voltage terminal of the device, and not under or below the high or low voltage terminal.

(19) In another example, the positioning is performed such that at least one, or a single, trench is located between gate and drain of the device. In another example, the positioning is performed such that at least one, or a single, trench is located only between gate and drain of the device, and not under or below the gate or drain. In an example, the positioning or alignment is performed such that the at least one, or the single, i.e. all, trench(es) which is/are located in between gate and drain of the device, are/is located only in between gate and drain of the device, and not under or below the gate or drain terminal.

(20) It will be appreciated that a high voltage terminal and low voltage terminal can correspond respectively to a drain and a gate of a transistor device. It will be appreciated that a high voltage terminal and low voltage terminal can correspond respectively to a cathode and an anode of a diode device. Typical values for those high and low voltages are known to the skilled person. A low voltage can for instance be a voltage below 10 V. A high voltage can for instance be a voltage above 10 V.

(21) In another example, the isolation patterns and the device are positioned or aligned in such a way that the gate of the device is located vertically above the isolation pattern, i.e. on top of the overgrown area. This has the advantage that the epitaxial material below the gate has lower dislocation density and results in more reliable devices.

(22) In another example, the trench is located at or beyond the periphery of the device, fully enclosing it (see FIG. 9f).

(23) In another example, isolation is done by deep trench etching (6a) through the III-nitride layers and into the Si substrate.

(24) In another example, trench etching is followed by thermal oxidation of the parts of the Si substrate that are uncovered by the trench etch (see FIG. 4).

(25) In another example, isolation is done by impurity implantation (in combination with trench etching or not).

(26) In another example, isolation is done by trench etching followed by a shallow implantation by plasma treatment.

(27) In another example, isolation is done by trench etching followed by thermal in-diffusion (into the Si) of impurities.

(28) Optionally the protective layer stack includes an etch stop layer such as below the SiN. This etch stop layer can comprise AlGaN. Both dry and wet etches in a fluorine chemistry will stop on the AlGaN layer with very high selectivity (see FIG. 5), so it allows for thorough removal of the remaining SiN without removing the AlGaN or any of the layers below. In this way thickness of the underlying layers can be kept very thin. In a preferred example, this etch stop layer is pure AlN and the AlN is then removed in a wet etch, e.g. in an alkaline solution or in resist developer, exposing the GaN layer (see FIG. 6). In another example, the AlN also contains also some Ga, and the removal is done in a controlled dry etch process (non-selective towards GaN).

(29) The remaining structure, containing the epitaxial layer stack terminated by the (In)Al(Ga)N functional layer and GaN cap respectively, is loaded into a reactor for re-growth (structure as depicted in FIG. 6). In a preferred example, the thickness of the GaN cap is at this point 2-10 nm thick, such as 5 nm, because it has been protected by the etch stop layer and this etch stop layer has been perfectly and completely selectively removed. Prior to re-growth, the layer stack is in an example heated up to high temperature under ammonia overflow. Under selected conditions, the GaN evaporates, typically at a rate of 2 nm/min-40 nm/min , such as 10 nm/min, exposing the top AlGaN layer of the buffer stack (see FIG. 7). As, to this point, an advantage obtained is that this layer has always been capped and as a result never been exposed to any possible source of contamination, its surface is in the right pristine condition to allow for epitaxial re-growth. The growth will in a first phase only occur on the surface between the STI trenches (see FIG. 8a). At a certain point, growth conditions are changed and the III-nitride layers will start to grow laterally (see FIG. 8b), so that the growth front is moving sideways over the trenches, eventually completely covering them and thus forming a continuous, coalesced layer (see FIG. 8c).

(30) In an example, the direction of the growth front on which the epitaxial layers grow is changed by tuning growth conditions, allowing the isolation patterns to be overgrown. These processes are well known by the person skilled in the art and are referred to as epitaxial lateral overgrowth (ELOG). The change of growth direction changes the way stress is built up in the growing layer and opens a new parameter space when depositing III-nitrides on foreign substrates. Usually stress engineering requires AlGaN interlayers to be inserted between AlN and GaN, but in an example this is no longer required.

(31) Growth may now continue to include active device layers on top of these overgrown structures (see FIG. 8d). In an example, the active device layers comprise a channel layer and a barrier layer. In an example, the channel layer comprises GaN or one of its alloys. In an example, the barrier layer, the barrier layer comprises AlGaN, InAlN, or InAlGaN. In another example, the channel and bather layer are capped by a SiN passivation layer. This SiN may be deposited by MOCVD, in the same epitaxial process as the channel and barrier layer.

(32) In another example, the active device layers comprise an n-type semiconductor layer, an active light-emitting layer stack and a p-type semiconductor layer. In an example, the n-type semiconductor layer comprises GaN or AlGaN or InGaN or alloys thereof, impurity doped with a suitable element, e.g. Si. In an example, the active light-emitting layer stack comprise one or more InAlGaN quantum well(s) separated from one another by InAlGaN barriers. In an example, the p-type semiconductor layer comprises GaN or AlGaN or InGaN or alloys thereof, impurity doped with a suitable element, e.g. Mg.

(33) In a preferred example, the active device is a transistor. The transistor is in an example defined as a HEMT device. Various types of HEMT devices are know from literature, e.g. PHEMT, E-HEMT, D-HEMT or DHFET.

(34) In another example, the active device is a diode. In another example, the active device is a light-emitting diode.

(35) Two or more of the above method steps, examples, dimensions, etc. may be combined in the present invention, depending on for instance requirements of a final device, transistor, etc.

(36) In an example, the processing of the active device starts with the formation of ohmic contacts. In an example, this is done by starting with deposition of photoresist and a lithography step defining the areas of the ohmic contacts and removing the passivation layer, if present. In an example this removal is done in a dry etching system based on fluorine chemistry, e.g. in an inductively coupled plasma system using SF.sub.6 or CF.sub.4 as etching gas and RF (or “platen”) and ICP (or “coil”) etching powers of 10 W and 150 W respectively. In a next step, a stack of metals is deposited, e.g. by thermal evaporation, or by sputtering, or by e-beam evaporation, comprising Ti and Al. In an example, the Ti and Al are further capped by another metal (such as a refractory metal or Ti or Ni) and Au.

(37) Metal patterns are consecutively defined by performing lift-off of the metal on top of the photoresist and not in contact with the barrier layer. In another example, the photoresist is first removed, then the metal stack comprising Ti and Al is deposited, and then a second photoresist deposition and photolithography step are done to allow dry etching of the metal stack in areas where it is unwanted and removing the photoresist. In an example, the thus defined metal patterns are subjected to an alloying steps, e.g. a rapid thermal annealing step for a duration of one minute in a reducing or inert atmosphere such as (hydrogen or forming gas or nitrogen gas) at a temperature between 800° C. and 900° C.

(38) In an example, the processing continues by defining the isolation patterns. This is done by performing photoresist deposition and a photolithography step. In an example the photoresist patterns thus formed act as a mask for the etching of a mesa, e.g. in a dry etching system based on chlorine chemistry, e.g. in an inductively coupled plasma system using Cl.sub.2 or BCl.sub.3 as etching gas and RF (or “platen”) and ICP (or “coil”) etching powers of 50 W and 150 W respectively. In another example, patterns thus formed act as a mask for impurity implantation, e.g. by implanting nitrogen, helium, hydrogen, boron, iron, or magnesium. In an example, the impurity implantation uses triple implantation steps, e.g. one step at an acceleration voltage of 30 keV, implanting a dose of 6 times 10.sup.12/cm2 of N.sup.14, a second step at an acceleration voltage of 160 keV, implanting a dose of 1.8 times 10.sup.13/cm2 of N.sup.14and a third step at an acceleration voltage of 400 keV, implanting a dose of 2.5 times 10.sup.13/cm2 of N.sup.14.

(39) In an example, the processing continues by the definition of the gate contact. In an example, this is done by starting with deposition of photoresist and a lithography step defining the foot of the gate contact and removing the passivation layer, if present. In an example this removal is done in a dry etching system based on fluorine chemistry, e.g. in an inductively coupled plasma system with a low damage etching process, e.g. using SF.sub.6 or CF.sub.4 as etching gas and RF (or “platen”) and ICP (or “coil”) etching powers of 10 W and 150 W respectively at a pressure of 20 mTorr. In an example, after the local removal of the SiN, the photoresist is removed and the exposed AlGaN barrier is subjected to recovery steps, e.g. by thermal annealing at a temperature between 300° C. and 600° C. in ammonia, or hydrogen, or oxygen, or nitrogen, or ozone or by plasma treatment in ammonia, or hydrogen, or oxygen, or nitrogen, or ozone chemistry.

(40) In an example, after the recovery step, photoresist deposition and a lithography step is performed, well aligned to the gate foot. Then the gate metal stack is deposited, e.g. comprising Ni, Pt, W, WN, or TiN and capped by Al, Au or Cu. Metal patterns are consecutively defined by performing lift-off of the metal on top of the photoresist and not in contact with the barrier layer. In another example, after the recovery step, the gate metal stack is deposited, e.g. comprising Ni, Pt, W, WN, or TiN and capped by Al, Au or Cu. Then photoresist deposition and a lithography step is performed, well aligned to the gate foot. The thus defined photoresist patterns act as a mask for the dry etching of the metal stack in areas where it is unwanted. Next the photoresist is removed. In an example, additional passivation layers are added. In an example, the passivation layer comprises SiN or Si-oxide, e.g. deposited by LPCVD, or PE-CVD or ICP-CVD. In an example, openings are made in the passivation layer to uncover the device terminals, by performing a photolithography step and etching the passivation layer, e.g. by wet etching in HF or buffered HF or by dry etching in an RIE or ICP plasma tool in a fluorine chemistry.

(41) In an example, additional metal interconnect layers are defined using methods known to a person skilled in the art, to allow low resistivity pathways for the gate, source and drain currents.