A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Provided is a polycrystalline ceramic substrate to be bonded to a compound semiconductor substrate with a bonding layer interposed therebetween, wherein at least one of relational expression (1) 0.7<α.sub.1/α.sub.2<0.9 and relational expression (2) 0.7<α.sub.3/α.sub.4<0.9 holds, where α.sub.1 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 300° C. and α.sub.2 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 300° C., and α.sub.3 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 1000° C. and α.sub.4 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 1000° C.

The present application discloses an epitaxial growth method for an FDSOI hybrid region, comprising: step 1, providing an FDSOI substrate structure, and forming a hard mask layer; step 2, forming a trench in the entire hybrid region, wherein the bottom surface of the trench is below or level with the top surface of the semiconductor body layer; step 3, performing oxidation to form a first oxide layer on the exposed surfaces of the semiconductor body layer and the semiconductor top layer; step 4, fully etching the first oxide layer, and forming an inner sidewall composed of the remaining first oxide layer on the side surface of the trench in a self-aligned manner; and step 5, performing epitaxial growth to form, in the trench, a semiconductor epitaxial layer in contact with the semiconductor body layer.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

A method for manufacturing a relaxed epitaxial InGaN layer from a GaN/InGaN substrate comprising the following steps: a) providing a first stack comprising a GaN or InGaN layer to be porosified and a barrier layer, b) transferring the GaN or InGaN layer to be porosified and the barrier layer to a porosification support, in such a way as to form a second stack, c) forming a mask on the GaN or InGaN layer to be porosified, d) porosifying the GaN or InGaN layer through the mask, e) transferring the GaN or InGaN porosified layer and the barrier layer to a support of interest, f) forming an InGaN layer by epitaxy on the barrier layer, whereby a relaxed epitaxial InGaN layer is obtained.

A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Various embodiments relate to an optical detection element and GOI (Ge-on-insulator) device for ultra-small on-chip optical sensing, and a manufacturing method of the same. According to various embodiments, the optical detection element and the GOI device may be implemented on a GOI structure comprising a germanium (Ge) layer, and the GOI device may be implemented to have an optical detection element. Specifically, the GOI device may include a GOI structure with a waveguide region comprising a germanium layer, a light source element configured to generate light for the waveguide region, and at least one optical detection element configured to detect light coming from the waveguide region. At least one slot configured to collect light from the light source element may be formed in the germanium layer in the waveguide region. The light source element may generate light so as to be coupled to the germanium layer in the waveguide region. The optical detection element may detect heat generated as light is propagated from the germanium layer.

A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.