A method for manufacturing an SOI wafer including a step of performing an adjustment to a film thickness of an SOI layer of the SOI wafer by wet etching. In the step of performing the adjustment to the film thickness of the SOI layer, a first etching step of etching a surface of the SOI layer using an SC1 solution; and a second etching step of etching the surface of the SOI layer by bringing the SOI layer into contact with ozone water to form an oxide film on the surface of the SOI layer and then bringing the formed oxide film into contact with an HF-containing aqueous solution to remove the oxide film, are performed in combination. The etchings are performed such that a removal amount of the SOI layer in the first etching step is smaller than that in the second etching step.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

A semiconductor device includes first and second insulating films and a semiconductor part. The semiconductor part is provided on the first insulating film and surrounded by the second insulating film. The semiconductor part includes first and fourth semiconductor layers of a first conductivity type, second and third semiconductor layers of a second conductivity type, and first to third contact regions provided respectively on the second to fourth semiconductor layer. The second to fourth semiconductor layers are arranged in a first direction on the first semiconductor layer. The fourth semiconductor layer is provided between the second and third semiconductor layers. The first and second contact regions being provided with first distances to the second insulating film in a second direction crossing the first direction. The first distances are less than a second distance in the second direction from the third contact region to the second insulating film.

After forming an epitaxial germanium layer over a germanium-on-insulator substrate including an insulator layer and a doped germanium layer overlying the insulator layer, the doped germanium layer is selectively removed and a passivation layer is formed within a space between the epitaxial germanium layer and the insulator layer that is formed by removal of the doped germanium layer. A lateral bipolar transistor is subsequently formed in the epitaxial germanium layer.

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w.sub.1), a contact trench having a second width (w.sub.2) and a capacitive trench having a third width (w.sub.3). Methods are described that allow the formation of the trenches in a normal process flow.

There is set forth herein an optoelectrical device, comprising: a substrate; an interposer dielectric stack formed on the substrate, the interposer dielectric stack including a base interposer dielectric stack, a photonics device dielectric stack, and a bond layer that integrally bonds the photonics device dielectric stack to the base interposer dielectric stack. There is set forth herein a method comprising building an interposer base structure on a first wafer having a first substrate, including fabricating a plurality of through vias in the first substrate and fabricating within an interposer base dielectric stack formed on the first substrate one or more metallization layers; and building a photonics structure on a second wafer having a second substrate, including fabricating one or more photonics devices within a photonics device dielectric stack formed on the second substrate.

A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

A semiconductor wafer in accordance with an embodiment includes: a support substrate semiconductor wafer having a first surface and a second surface opposite to the first surface; and an active layer formed on the first surface. The support substrate semiconductor wafer includes a support substrate semiconductor and an insulating film which is formed on a first surface side and a second surface side of the support substrate semiconductor. An area of the insulating film of the second surface is smaller than an area of the insulating film of the first surface.