A capping layer is on top of a substrate. A first low-k dielectric layer is on top of the capping layer. One or more trenches are within the first low-k dielectric layer. Each of the one or more trenches have a same depth. Each trench of the one or more trenches include a barrier layer on top of the first low-k dielectric layer, a liner layer and a metal layer on top of the liner layer.

A semiconductor structure includes: a base, including a substrate, a first isolation layer, a first dielectric layer, and a stop layer that are formed in a stack manner, a first contact hole being formed in the base; a first insulating layer and a first barrier layer sequentially formed on an inner wall of the first contact hole, a first contact structure being disposed in the first contact hole; a protective layer covering an upper surface of the first contact structure; a second dielectric layer and a second isolation layer sequentially stacked on the protective layer, a second contact hole being formed in the base; and a second barrier layer formed on an inner wall of the second contact hole and a second contact structure disposed in the second contact hole.

Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.

A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.

A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.

A film formation method for selectively forming a film on a substrate includes: a preparation step of preparing a substrate having a surface on which a first film and a second film are exposed; a first film forming step of supplying a compound for forming a self-assembled monolayer onto the substrate to form the self-assembled monolayer on the first film, the compound having a functional group including fluorine and carbon and suppressing formation of a third film; a second film forming step of forming the third film on the second film; and a first removal step of removing the third film formed in a vicinity of the self-assembled monolayer by irradiating the surface of the substrate with ions or active species, wherein the third film is a film which forms a volatile compound more easily than the first film by being bonded to fluorine and carbon in the self-assembled monolayer.

A for preparing a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, and forming an etch stop layer over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer, and forming a first metal plug penetrating through the second dielectric layer, the etch stop layer and the first dielectric layer. The first metal plug protrudes from the second dielectric layer. The method further includes performing an anisotropic etching process to partially remove the first metal plug such that the first metal plug has a convex top surface, and forming a third dielectric layer covering the second dielectric layer and the convex top surface of the first metal plug. In addition, the method includes forming a second metal plug over the first metal plug.

In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including a plurality of connection patterns on different levels and electrically connected to the circuit element, and a lower insulating structure covering the circuit element and the circuit interconnection structure; and an upper structure including an upper substrate in contact with an upper surface of the lower insulating structure, a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction.