A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.

An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a plurality of first conductive features adjacent to a top surface of the first semiconductor structure, a second semiconductor structure positioned above the first semiconductor structure and including a plurality of second conductive features adjacent to a bottom surface of the second semiconductor structure, and a connection structure positioned between the first semiconductor structure and the second semiconductor structure. The connection structure includes a connection layer electrically coupled to the plurality of first conductive features and the plurality of second conductive features, and a plurality of first porous interlayers positioned between the plurality of first conductive features and the plurality of second conductive features. A porosity of the plurality of first porous interlayers is between about 25% and about 100%.

A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.

An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Embodiments of the present disclosure provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a base including an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, a top opening area of the first isolation structure being greater than that of the second isolation structure; the first isolation structure having a first groove, and a first insulation structure configured to fill the first groove; and the first insulation structure including at least a top isolation layer, a top surface of the top isolation layer being flush with a top surface of the base, and the top isolation layer being made of at least a low dielectric constant material.

Tiered-profile contacts for semiconductor devices and techniques for formation thereof are provided In one aspect, a method for forming tiered-profile contacts to a semiconductor device includes: depositing a first oxide layer over the semiconductor device; depositing a second oxide layer on the first oxide layer; patterning contact trenches through the first/second oxide layer down to the semiconductor device; isotropically etching a top portion of the contact trenches selective to a bottom portion of the contact trenches based on the second oxide layer having a greater etch rate than the first oxide layer to make the top portion of the contact trenches wider than the bottom portion; and filling the contact trenches with a contact metal(s) to form the tiered-profile contacts. Other methods to form tiered-profile contacts using sacrificial spacers as well as structures including the present tiered-profile contacts are also provided.

The present application discloses a method for fabricating a semiconductor device with a connection structure. The method includes providing a first semiconductor structure comprising a plurality of first conductive features adjacent to a top surface of the first semiconductor structure; forming a connection structure comprising a connection insulating layer on the top surface of the first semiconductor structure, a connection layer in the connection insulating layer, and a plurality of first porous interlayers on the plurality of first conductive features and in the connection insulating layer; and forming a second semiconductor structure comprising a plurality of second conductive features on the plurality of first porous interlayers

An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

A method for manufacturing a semiconductor device includes forming a first dielectric layer, and forming a second dielectric layer stacked on the first dielectric layer. In the method, a plurality of conductive lines are formed in the first and second dielectric layers, and the plurality of conductive lines are recessed to form a plurality of openings in the second dielectric layer. The method also includes forming a plurality of dielectric fill layers on the plurality of conductive lines in the plurality of openings. At least one of the plurality of dielectric fill layers is selectively removed with respect to the second dielectric layer to expose a conductive line of the plurality of conductive lines, and a via is formed in place of the selectively removed dielectric fill layer.