A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.

A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.

Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.

A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.

A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.

A compound semiconductor device comprises a substrate, comprising a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface comprises a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein the first and second deteriorated surfaces are rougher than at least one of the first crack surface, the second crack surface and the third crack surface; and wherein the second crack surface is about perpendicular to the top surface, and the third crack surface is about perpendicular to the bottom surface.

Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.

Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.

The chip manufacturing method includes: a preparing step of preparing a substrate 1 having a plurality of elements 2; a defining step of defining, based on information regarding a satisfactory element 2a and/or a defective element 2b, an arrangement of chips 10 each composed of two or more adjacent ones of the elements 2 such that the number of the chips 10 that include only the satisfactory elements 2a is larger than in the case of dividing the substrate 1 into a plurality of the chips 10 along virtual dicing lines formed assuming that the defective element 2b does not exist; a mask forming step of forming, based on the defined arrangement of the chips 10, a mask 20 that has openings 20a and that covers the chips 10; and a dividing step of dividing the substrate 1 into a plurality of the chips 10 by plasma etching.