H01L21/786

SOI substrate and related methods

Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

SOI substrate and related methods

Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

SEMICONDUCTOR DEVICE PACKAGE

A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.

SEMICONDUCTOR DEVICE PACKAGE

A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.

Method for manufacturing light emitting device
10672945 · 2020-06-02 · ·

A method of manufacturing a light emitting device includes: a first wafer preparation step including preparing, on a first substrate, m first wafers (where m2), each of the first wafers comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a second wafer preparation step including bonding a second substrate with the second semiconductor layer of a first of the m first wafers and then removing the first substrate from the first wafer, so as to form a second wafer in which the first semiconductor layer is exposed; and a first bonding step including bonding the first semiconductor layer exposed at the surface of the second wafer and the second semiconductor layer of a second of the m first wafers together using a light-transmissive conductive layer, and then removing a first substrate of the second of the m first wafers.

Method for manufacturing light emitting device
10672945 · 2020-06-02 · ·

A method of manufacturing a light emitting device includes: a first wafer preparation step including preparing, on a first substrate, m first wafers (where m2), each of the first wafers comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a second wafer preparation step including bonding a second substrate with the second semiconductor layer of a first of the m first wafers and then removing the first substrate from the first wafer, so as to form a second wafer in which the first semiconductor layer is exposed; and a first bonding step including bonding the first semiconductor layer exposed at the surface of the second wafer and the second semiconductor layer of a second of the m first wafers together using a light-transmissive conductive layer, and then removing a first substrate of the second of the m first wafers.

Cutting method of workpiece
10658218 · 2020-05-19 · ·

In a cutting method of a workpiece, a half-cut groove having a groove bottom that reflects light of an epi-illumination part is formed in a range of a peripheral surplus region of a planned dividing line that has not been cut, and the half-cut groove is detected with discrimination from a laser-processed groove that diffusely reflects the light and is darkly displayed.

Cutting method of workpiece
10658218 · 2020-05-19 · ·

In a cutting method of a workpiece, a half-cut groove having a groove bottom that reflects light of an epi-illumination part is formed in a range of a peripheral surplus region of a planned dividing line that has not been cut, and the half-cut groove is detected with discrimination from a laser-processed groove that diffusely reflects the light and is darkly displayed.

Electronic Device Including a Contact Structure Contacting a Layer

An electronic device can include a semiconductor layer and a contact structure forming an ohmic contact with the layer. In an embodiment, the semiconductor layer can include a III-N material, and the contact structure includes a first phase and a second phase, wherein the first phase includes Al, the second phase includes a metal, and the first phase contacts the semiconductor layer. In another embodiment, the semiconductor layer can be a monocrystalline layer having a surface along a crystal plane. The contact structure can include a polycrystalline material including crystals having surfaces that contact the surface of the monocrystalline layer, wherein a lattice mismatch between the surface of the monocrystalline layer and the surfaces of the crystals is at most 20%.

Electronic Device Including a Contact Structure Contacting a Layer

An electronic device can include a semiconductor layer and a contact structure forming an ohmic contact with the layer. In an embodiment, the semiconductor layer can include a III-N material, and the contact structure includes a first phase and a second phase, wherein the first phase includes Al, the second phase includes a metal, and the first phase contacts the semiconductor layer. In another embodiment, the semiconductor layer can be a monocrystalline layer having a surface along a crystal plane. The contact structure can include a polycrystalline material including crystals having surfaces that contact the surface of the monocrystalline layer, wherein a lattice mismatch between the surface of the monocrystalline layer and the surfaces of the crystals is at most 20%.