Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

A semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and first to fourth wirings. The first transistor includes a first gate and a second gate, and one of a source and a drain of the first transistor is connected to the first wiring and the second gate, and the other of the source and the drain is connected to one of a source and a drain of the second transistor and one electrode of the capacitor. A gate of the second transistor is connected to the other electrode of the capacitor, and the other of the source and the drain of the second transistor is electrically connected to the second wiring. The first wiring is supplied with a first potential, and the second wiring is supplied with a second potential and a third potential alternately. The third wiring is connected to the first gate and supplied with a first signal. The fourth wiring is connected to the gate of the second transistor and supplied with a second signal obtained by inverting the first signal.

Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.

Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.

[Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.

[Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.

A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.

A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.