An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

A matching circuit which can handle a plurality of frequencies is provided. The matching circuit includes a transistor and an inductor. The matching circuit uses capacitance formed between a gate and a source/drain (referred to as capacitance Cgsd below) of the transistor as a condenser. The capacitance Cgsd changes with the voltage of the gate with respect to the source (referred to as voltage Vgs below). The transistor included in the matching circuit is an OS transistor including a metal oxide in a channel formation region. The OS transistor features larger variation in capacitance Cgsd with respect to the voltage Vgs than the MOSFET that uses silicon, which enables the matching circuit to handle alternating-current signals in a wide frequency range.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

A method of manufacturing a flexible display includes providing a substrate having a first and second pad density areas and a pair of long sides; forming conductive pads on the substrate, each of the conductive pad is free of right angle and in a shape of parallelogram, and a pad density of the second pad density area is higher than that of the first pad density area; providing a flexible substrate; and bonding the conductive pads to a conductor of a circuit of the flexible substrate. Each of the conductive pad has long sides and short sides, a portion of the conductive pads have the long sides sloped away from the first pad density area and toward one long side of the substrate, and the rest of the conductive pads have the long sides sloped away the first pad density area and toward the other long side of the substrate.

A method of manufacturing a flexible display includes providing a substrate having a first and second pad density areas and a pair of long sides; forming conductive pads on the substrate, each of the conductive pad is free of right angle and in a shape of parallelogram, and a pad density of the second pad density area is higher than that of the first pad density area; providing a flexible substrate; and bonding the conductive pads to a conductor of a circuit of the flexible substrate. Each of the conductive pad has long sides and short sides, a portion of the conductive pads have the long sides sloped away from the first pad density area and toward one long side of the substrate, and the rest of the conductive pads have the long sides sloped away the first pad density area and toward the other long side of the substrate.

Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source/drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source/drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.

A comparator circuit includes a first comparator configured to receive input of an input signal and a comparison target signal to be compared with the input signal, a first output stage including an N-channel transistor having a control terminal to which a first control terminal voltage output from the first comparator is applied, and a first clamp unit configured to limit the first control terminal voltage to be not higher than a first predetermined voltage that is higher than a first threshold voltage of the N-channel transistor but is lower than a first high side voltage output as high level from the first comparator when the first control terminal voltage is not limited.

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.