A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

A semiconductor device polysilicon resistor formation method is provided. A third ion implantation and a fourth ion implantation are performed in a polysilicon resistor region, so that a high-resistance polysilicon resistor can be formed without an additional mask process.

A semiconductor device including a protected element, a contact region, wiring, and a channel stopper region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. The periphery of the diode is surrounded by an element isolation region. The contact region is arranged at a portion on a main face of the anode region, and is set with a same conductivity type as the anode region, and set with a higher impurity concentration than the anode region. The wiring is arranged over the diode. One end portion of the wiring is connected to the contact region and another end portion extends over a passivation film. The channel stopper region is arranged at a portion on the main face of the anode region under the wiring between the contact region and the element isolation region, and is set with an opposite conductivity type to the contact region.

The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.