A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.

An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.

The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

A Compact CMOS System having a non-split Channel Regions Controlling Gate, including a material which forms rectifying junctions with both N and P-type Field Induced Semiconductor, and at least two Channels electrically connected thereto and projecting substantially away therefrom adjacent and parallel to one another. There further being substantially non-rectifying junctions to the material which forms a rectifying junction with both N and P-type Field Induced Semiconductor, and to distal ends of the at least two Channels.