An apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.

An apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.

A TFT structure based on a flexible multi-layer graphene quantum carbon substrate material and a method for manufacturing the same. The TFT structure includes a multi-layer graphene quantum carbon substrate, a first source, a first drain, a first gate insulating layer, and a first gate. The multi-layer graphene quantum carbon substrate includes a first channel area, and a first drain area and a first source area that are located at corresponding recessed positions on the multi-layer graphene quantum carbon substrate that are separated from each other. The first channel area is located between the first drain area and the first source area, the first source is filled in the first source area, the first drain is filled in the first drain area, the first gate insulating layer is disposed on the first channel area, and the first gate is disposed on the first gate insulating layer.

A TFT structure based on a flexible multi-layer graphene quantum carbon substrate material and a method for manufacturing the same. The TFT structure includes a multi-layer graphene quantum carbon substrate, a first source, a first drain, a first gate insulating layer, and a first gate. The multi-layer graphene quantum carbon substrate includes a first channel area, and a first drain area and a first source area that are located at corresponding recessed positions on the multi-layer graphene quantum carbon substrate that are separated from each other. The first channel area is located between the first drain area and the first source area, the first source is filled in the first source area, the first drain is filled in the first drain area, the first gate insulating layer is disposed on the first channel area, and the first gate is disposed on the first gate insulating layer.

A capacitive device includes: a first metal plate; a first planar dielectric layer disposed on the first metal plate; a second planar dielectric layer disposed on the first planar dielectric layer; a third planar dielectric layer disposed on the second planar dielectric layer; and a second metal plate disposed on the third planar dielectric layer; wherein the first planar dielectric layer has a first dielectric constant, the second planar dielectric layer has a second dielectric constant, and the third planar dielectric layer has a third dielectric constant, and the second dielectric constant is different from the first dielectric constant and the third dielectric constant, the second planar dielectric layer includes Tantalum pentoxide.

A capacitive device includes: a first metal plate; a first planar dielectric layer disposed on the first metal plate; a second planar dielectric layer disposed on the first planar dielectric layer; a third planar dielectric layer disposed on the second planar dielectric layer; and a second metal plate disposed on the third planar dielectric layer; wherein the first planar dielectric layer has a first dielectric constant, the second planar dielectric layer has a second dielectric constant, and the third planar dielectric layer has a third dielectric constant, and the second dielectric constant is different from the first dielectric constant and the third dielectric constant, the second planar dielectric layer includes Tantalum pentoxide.

A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.