FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

A thin-film resistor and a method for fabricating a thin-film resistor are provided. The thin-film resistor comprises a first terminal, a second terminal, and a resistor body providing a resistive current path between the first terminal and the second terminal, and the method comprises depositing a first layer of conductive material onto at least one of the supporting structure and the resistor body, applying a first lithographic mask to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the supporting structure and the resistor body, applying a second lithographic mask to the second layer, and etching the second layer to form the second terminal, wherein the first lithographic mask is different to the second lithographic mask, and a lateral separation of the first terminal and the second terminal is less than an in-plane minimum feature size of the first and second lithographic masks

A thin-film resistor and a method for fabricating a thin-film resistor are provided. The thin-film resistor comprises a first terminal, a second terminal, and a resistor body providing a resistive current path between the first terminal and the second terminal, and the method comprises depositing a first layer of conductive material onto at least one of the supporting structure and the resistor body, applying a first lithographic mask to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the supporting structure and the resistor body, applying a second lithographic mask to the second layer, and etching the second layer to form the second terminal, wherein the first lithographic mask is different to the second lithographic mask, and a lateral separation of the first terminal and the second terminal is less than an in-plane minimum feature size of the first and second lithographic masks

This disclosure relates to a semiconductor die and a method for fabrication of a semiconductor die. The disclosed semiconductor die comprises a substrate having a drain-cathode region, a plurality of trenches and mesas, a first anode trench, and a first floating closed loop mesa surrounding the first anode trench. The semiconductor die further comprises a first anode region under the first anode trench, a plurality of source regions extending from top surfaces into the plurality of mesas, and a plurality of gate regions extending along a bottom surface and portions of sidewalls of each of the plurality of trenches. The first floating closed loop mesa electrically isolates the first anode region from the plurality of gate regions, and the first anode region electrically couples to the plurality of source regions to integrate an anti-parallel diode cell within vertical junction field-effect transistors (JFETs).

This disclosure relates to a semiconductor die and a method for fabrication of a semiconductor die. The disclosed semiconductor die comprises a substrate having a drain-cathode region, a plurality of trenches and mesas, a first anode trench, and a first floating closed loop mesa surrounding the first anode trench. The semiconductor die further comprises a first anode region under the first anode trench, a plurality of source regions extending from top surfaces into the plurality of mesas, and a plurality of gate regions extending along a bottom surface and portions of sidewalls of each of the plurality of trenches. The first floating closed loop mesa electrically isolates the first anode region from the plurality of gate regions, and the first anode region electrically couples to the plurality of source regions to integrate an anti-parallel diode cell within vertical junction field-effect transistors (JFETs).

A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.