A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer. The FinFET transistor comprising: a fin semiconductor structure comprising an elongate protruding core portion, the fin semiconductor structure being arranged on the lattice-mismatched semiconductor epilayer, a first and a second nanostructured electrode radially enclosing respectively a source end and a drain end of the protruding core portion, and a nanostructured gate electrode radially enclosing a central portion of the protruding core portion, the central portion being a portion of the protruding core portion between the source end and the drain end.

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

The current disclosure describes semiconductor devices, e.g., transistors including a thin semimetal layer as a channel region over a substrate, which includes bandgap opening and exhibits semiconductor properties. Described semiconductor devices include source/drain regions that include a thicker semimetal layer over the thin semimetal layer serving as the channel region, this thicker semimetal layer exhibiting metal properties. The semimetal used for the source/drain regions include a same or similar semimetal material as the semimetal of the channel region.

A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

A method of manufacturing an electronic circuit comprising a first device and at least a second device is disclosed. The first device comprises a first terminal, a second terminal, and a first body of semiconductive material providing a semiconductive path between the first and second terminals, and the second device comprises a third terminal, a fourth terminal, and a second body of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal. The method comprises: forming the first body; and forming the second body, wherein the first body comprises a first quantity of a metal oxide and the second body comprises a second quantity of said metal oxide. Corresponding electronic circuits are disclosed.

A method of manufacturing an electronic circuit comprising a first device and at least a second device is disclosed. The first device comprises a first terminal, a second terminal, and a first body of semiconductive material providing a semiconductive path between the first and second terminals, and the second device comprises a third terminal, a fourth terminal, and a second body of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal. The method comprises: forming the first body; and forming the second body, wherein the first body comprises a first quantity of a metal oxide and the second body comprises a second quantity of said metal oxide. Corresponding electronic circuits are disclosed.

A thin-film resistor and a method for fabricating a thin-film resistor are provided. The thin-film resistor comprises a first terminal, a second terminal, and a resistor body providing a resistive current path between the first terminal and the second terminal, and the method comprises depositing a first layer of conductive material onto at least one of the supporting structure and the resistor body, applying a first lithographic mask to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the supporting structure and the resistor body, applying a second lithographic mask to the second layer, and etching the second layer to form the second terminal, wherein the first lithographic mask is different to the second lithographic mask, and a lateral separation of the first terminal and the second terminal is less than an in-plane minimum feature size of the first and second lithographic masks