A semiconductor device includes first to tenth transistors and first to fourth capacitors. Gates of the first and the fourth transistors are electrically connected to each other. First terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor. A second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. Gates of the second, seventh, and tenth transistors are electrically connected to first terminals of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor.

Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels.

In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels.

A semiconductor structure for RF applications comprises: a first μTP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes an oxide, a first conductor and a second conductor over the oxide, a first insulator over the first conductor, a second insulator over the second conductor, a third conductor over the first insulator, a fourth insulator over the second insulator, a fifth insulator over the third insulator and the fourth insulator, a sixth insulator over the fifth insulator, a seventh insulator that is over the oxide and placed between the first conductor and the second conductor, an eighth insulator over the seventh insulator, a third conductor over the eighth insulator, and a ninth insulator over the third conductor and the sixth to eighth insulators. The third conductor includes a region overlapping the oxide. The seventh insulator includes a region in contact with each of the oxide, the first conductor, the second conductor, and the first to sixth insulators. The first insulator, the second insulator, the fifth insulator, and the ninth insulator are each a metal oxide having an amorphous structure.

A display apparatus with high display quality is provided. A high-resolution display apparatus is provided. The display apparatus includes a plurality of pixels, and the pixels each include a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor. A gate of the second transistor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor. One frame period of each of the pixels includes a period in which the first transistor and the fourth transistor are each in a conduction state.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.

Disclosed herein are integrated circuit (IC) structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. One example IC structure includes an III-N transistor in a first layer over a support structure (e.g., a substrate) and a TFT in a second layer over the support structure, where the first layer is between the support structure and the second layer. Another example IC structure includes a III-N semiconductor material and a TFT, where at least a portion of a channel material of the TFT is over at least a portion of the III-N semiconductor material.

A data device with a small circuit area and reduced power consumption is used. The data processing device includes a NAND memory portion and a controller. The memory portion includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell.