An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

In certain examples, methods and semiconductor structures are directed to a method comprising steps of forming by monolithically integrating or seeding via polycrystalline diamond (PCD) particles on a GaN-based layer characterized as including GaN in at least a surface region of the GaN-based layer. After the step of seeding, the PCD particles are grown under a selected pressure to form a diamond layer section and to provide a semi-conductive structure that includes the diamond layer section integrated on or against the surface region of the GaN-based layer.

An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.

IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

A semiconductor device that is suitable for high integration is provided. A first layer provided with a first transistor including an oxide semiconductor, over a substrate; a second layer over the first layer; a third layer provided with a second transistor including an oxide semiconductor, over the second layer; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer are included. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.

An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.

Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.