A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

Various heatsink arrangements, and methods for implementing and using such are discussed.

A grid array connector system is provided that includes cables that are mounted on a board which has a chip packaged mounted thereon. The cables include conductors that are connected to support vias positioned in openings in the board and the conductors are connected to the support vias. The board can be connected to a second board which provides a stiffening ring. The board can be connected to the second board by deflectable terminals which are press-fit into the second board.

A solid-state storage device includes a housing, a wiring board and a semiconductor package unit. The housing is formed with a heat-dissipating recess thereon. The wiring board is fixed in the housing. One side of the semiconductor package unit is mounted on the wiring board, and the other side of the semiconductor package unit is embedded in the heat-dissipating recess. A top surface and lateral surfaces surrounding the top surface of the semiconductor package unit are all thermally connected to the housing in the heat-dissipating recess.

A processing unit disposed within a compute unit, where the compute unit includes a printed circuit board (PCB) that includes an integrated circuit; a first thermal management device, that includes a first vapor chamber thermally conductively coupled to a first side of the integrated circuit; and a first heatsink thermally conductively coupled to the first vapor chamber; and a second thermal management device, that includes a second vapor chamber; and a second heatsink thermally conductively coupled to the second vapor chamber, where the second thermal management device is thermally conductively coupled to the first thermal management device; where the PCB is interposed between the first thermal management device and the second thermal management device.

A module. In some embodiments, the module includes a substrate; a plurality of electronic components, secured to an upper surface of the substrate; a thermally conductive heat spreader, on the electronic components and in thermal contact with an electronic component of the plurality of electronic components; a standoff, between the substrate and the heat spreader; an alignment element, extending into the substrate; a hard stop, under the substrate; and a plurality of compressible interconnects, under the substrate, and extending through the hard stop. The electronic components may be within a sight area of the substrate. The module may be configured to transmit a compressive load from an upper surface of the standoff to a lower surface of the substrate through a load path not including any of the electronic components.

The load force bolster assembly includes a metallic stiffener. A carrier associated with a CPU (Central Processing Unit) is located upon the load force bolster assembly and positioned upon the electrical connector. A heat sink is located upon both the carrier and the load force bolster assembly wherein a torsioned wire of the bolster assembly provides a downward force upon an up-and-down movable stud which is secured to a screw of the heat sink so as to downwardly push the heat sink, thus enhancing the normal forces among the heat sink, the CPU and the contacts of the electrical connector. To efficiently hold the torsioned wire in position around a bottom corner of the stiffener, a retention groove is formed around the top portion of the restricting pole, and a pressing ring is downwardly snapped into the retention groove so as to restrain the torsioned wire in position.

The present invention provides a chip packaging method, which includes: providing a base material, which includes plural finger contacts; disposing plural chips on the base material by flip chip mounting technology, and disposing plural vertical heat conducting elements surrounding each of the chips to connect the finger contacts on the base material; providing a packaging material to encapsulate the base material, the chips, and the vertical heat conducting elements; adhering a metal film on the packaging material via an adhesive layer, to form a package structure; and cutting the package structure into plural chip package units, wherein each of the chip package units includes one of the chips, a portion of the base material, a portion of the metal film, and a portion of the vertical heat conducting elements surrounding the chip.

A semiconductor device according to the present invention includes a cooler, a semiconductor package provided on an upper surface of the cooler, a metal plate having a main section provided on an upper surface of the semiconductor package, a spring that is provided above the main section and presses the main section toward the upper surface of the semiconductor package with an elastic force and a fixture that fixes the spring to an upper surface of the main section with the spring exerting the elastic force, wherein a surface, which faces the upper surface of the semiconductor package, of the main section is flat.

A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.