An integrated circuit (IC) that includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the front side surface. An inductive structure is located within a deep trench formed in the circuit substrate below the backside surface. The inductive structure is coupled to the active circuitry.

A semiconductor device includes a silicon die having a first side and a second side, an adhesive layer attached to the first side of the silicon die, and a lead frame. The lead frame comprises a die attach pad having a mounting surface. The mounting surface has a smaller area than an area of the adhesive layer. The silicon die is mounted on the lead frame at the mounting surface so that edges of the silicon die and the adhesive layer overhang the die attach pad without touching the die attach pad. The semiconductor device further includes one or more leads that are spaced apart from the edges of the silicon die and the adhesive layer.

A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.

A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.

A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a partial thickness of the lead frame strip metal. A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a half thickness of the lead frame strip metal.

A method includes forming a first magnetic material on a first surface of a conductive loop, forming a second magnetic material on a second surface of the conductive loop opposite the first surface to form an inductor, attaching a semiconductor die to a leadframe, and attaching the inductor to the leadframe with solder balls. The semiconductor die is between the inductor and the leadframe. The conductive loop: spans parallel to the leadframe; or is between the first magnetic material and the second magnetic material.

When a power semiconductor device is energized, heat generated from upper-side power semiconductor chips mounted on a P-potential electrode transfers to a first heat mass portion and a second heat mass portion, and heat generated from lower-side power semiconductor chips mounted on a intermediate potential electrode transfers to a resistor. A lead frame, the power semiconductor chip, an inner lead and the resistor are placed in symmetry with respect to a centerline, which can reduce the difference among the temperature increases of the power semiconductor chips when energized. In this way, transient temperature increase of the power semiconductor chip can be suppressed without adding a new member, such as a heat diffusion plate.

The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.

According to one embodiment, there is provided a semiconductor device including a first wiring, a semiconductor chip, a first bonding member, having a first melting temperature, located between the first wiring and the semiconductor chip, and a second wiring including a first connection unit and a second connection unit spaced from the first connection unit. A second bonding member having a second melting temperature higher than the first melting temperature is located between the semiconductor chip and the first connection unit. A third wiring is also provided, and a third bonding member having a third melting temperature lower than the second melting temperature is located between the second connection unit and the third wiring.