Cavity based feature on chip carrier

Abstract

A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.

Claims

1. A package, comprising: an electronic chip with at least one electric contact structure; an electrically conductive chip carrier having at least one coupling cavity; a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier, wherein the at least one electric contact structure comprises a pad and a pillar on the pad.

2. The package according to claim 1, wherein the electronic chip is mounted on the chip carrier in a flip chip configuration.

3. The package according to claim 1, wherein at least part of a surface of the at least one coupling cavity comprises at least one, but not limited to one, of the following surface finishes: an electric connection-promoting plating; an electric connection-promoting configuration of a bare metal surface, in particular a bare copper surface; an electric connection-promoting pre-plating; and an electric connection-promoting deposited material.

4. The package according to claim 1, comprising an encapsulant, in particular a mold compound, encapsulating at least part of the electronic chip and at least part of the chip carrier.

5. The package according to claim 4, wherein at least part of a surface of the chip carrier encapsulated by the encapsulant is configured to have a higher adhesiveness for material of the encapsulant than an adjacent surface, in particular than a surface of the chip carrier in the at least one coupling cavity.

6. The package according to claim 5, wherein at least part of the surface with the locally higher adhesiveness comprises at least one of the following surface finishes: an adhesiveness promoting configuration of a bare metal surface, in particular a bare copper surface; an adhesiveness promoting pre-plating; and an adhesiveness promoting roughening of the surface.

7. The package according to claim 1, wherein the coupling structure comprises a plated cap integrally formed on the pillar.

8. The package according to claim 1, wherein the pillar is configured without integrated cap.

9. The package according to claim 1, wherein the coupling structure comprises at least one solder bump.

10. The package according to claim 1, wherein the coupling structure located in one coupling cavity electrically contacts at least two separate electrically conductive pillars on a common pad of the at least one electric contact structure.

11. The package according to claim 1, wherein the chip carrier comprises or consists of a leadframe, for example a copper leadframe.

12. The package according to claim 1, further comprising: a further electronic chip with at least one further electric contact structure; a further coupling structure located at least partially in at least one further coupling cavity and electrically contacting the at least one further electric contact structure with the chip carrier.

13. The package according to claim 1, wherein the at least one coupling cavity delimits an entirely round surface portion of the chip carrier.

14. The package according to claim 1, wherein the coupling structure comprises at least one of the group consisting of: a solder structure; an electrically conductive adhesive; and a sinter structure.

15. A package, comprising: an electronic chip with at least one electric contact structure; a chip carrier having a first surface portion being geometrically adapted to have a higher wettability for coupling material than an adjacent surface, and having a second surface portion, having a higher adhesiveness for encapsulant material than an adjacent surface; a coupling structure located at least partially on the first surface portion and electrically contacting at least one electric contact structure with the chip carrier; an encapsulant encapsulating at least part of the electronic chip and covering at least part of the second surface portion, wherein the at least one electric contact structure comprises a pad and a pillar on the pad.

16. The package according to claim 15, wherein the first surface portion forms at least part of a coupling cavity.

17. The package according to claim 15, wherein the coupling material comprises at least one of the group consisting of: a solder material; an electrically conductive adhesive; and a sinter material.

18. A method of manufacturing a package, the method comprising: providing an electronic chip with at least one electric contact structure comprising a pad and a pillar on the pad; providing an electrically conductive chip carrier with at least one coupling cavity; coupling a coupling structure at least partially in the at least one coupling cavity to thereby electrically contact the at least one electric contact structure with the chip carrier.

19. The method according to claim 18, wherein the at least one coupling cavity is formed by at least one of the group consisting of etching and stamping the chip carrier.

20. The method according to claim 18, wherein the coupling structure has a larger lateral extension than a corresponding one of the at least one coupling cavity prior to the coupling in the at least one coupling cavity.

21. The method according to claim 18, wherein the method further comprises providing a flux in the at least one coupling cavity for activating a surface of the chip carrier in the at least one coupling cavity prior to coupling the coupling structure in the at least one coupling cavity.

22. The method according to claim 18, wherein the coupling comprises at least one of the group consisting of: soldering; adhering an electrically conductive adhesive; and sintering.

23. A method of manufacturing a package, the method comprising: providing an electronic chip with at least one electric contact structure comprising a pad and a pillar on the pad; providing an electrically conductive chip carrier with a first surface portion being geometrically adapted to have a higher wettability for coupling material than an adjacent second surface portion, and with the second surface portion, having a higher adhesiveness for encapsulant material than the adjacent first surface portion; coupling a coupling structure at least partially on the first surface portion to thereby electrically contact the at least one electric contact structure with the chip carrier; encapsulating at least part of the electronic chip and the second surface portion by an encapsulant.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments of the invention and constitute a part of the specification, illustrate exemplary embodiments of the invention.

[0049] In the drawings:

[0050] FIG. 1 illustrates a cross-section of a package according to an exemplary embodiment.

[0051] FIG. 2 to FIG. 4 illustrate cross-sections of structures obtained during carrying out a method of manufacturing a package according to an exemplary embodiment.

[0052] FIG. 5 illustrates a cross-section of a part of a package according to an exemplary embodiment.

[0053] FIG. 6 illustrates a cross-section of an intermediate structure obtained during manufacturing a package according to an exemplary embodiment.

[0054] FIG. 7 illustrates a cross-section of another intermediate structure obtained during manufacturing a package according to an exemplary embodiment.

[0055] FIG. 8 and FIG. 9 illustrate cross-sections of intermediate structures obtained during manufacturing a package according to an exemplary embodiment.

[0056] FIG. 10 illustrates a cross-section of a package according to an exemplary embodiment.

[0057] FIG. 11 shows a package according to yet another exemplary embodiment in which two electronic chips are mounted on a common chip carrier having multiple solder cavities.

[0058] FIG. 12 is a plane view of a rectangular coupling cavity and a circular coupling cavity in a respective chip carrier in combination with a group of parallel pillars according to exemplary embodiments of the invention.

[0059] FIG. 13 shows a portion of a chip carrier with a coupling cavity in which flux has been dispensed to promote a subsequent solder connection according to an exemplary embodiment.

[0060] FIG. 14 illustrates a cross-section of a structure obtained during carrying out a method of manufacturing a package according to an exemplary embodiment.

[0061] FIG. 15 illustrates a cross-section of a part of a package according to an exemplary embodiment formed in accordance with FIG. 14.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0062] The illustration in the drawing is schematically drawn and not to scale.

[0063] Before exemplary embodiments are described in more detail referring to the figures, some general considerations will be summarized based on which exemplary embodiments have been developed.

[0064] According to an exemplary embodiment of the invention, cavity based flip chip soldering may be implemented. This may allow to overcome a conventional shortcoming related to the phenomenon of solder bleed out of flip chip die attach systems. The mentioned embodiment of the invention addresses the technical challenge that a leadframe surface should preferably offer a trade-off between good wetting, control of the solder bleed out, and a good adhesion to the mold compound.

[0065] Consequences of uncontrolled solder bleed out may be at least one of inconsistent bond line thickness, variation in solder joint quality and/or reliability, variation in mold compound adhesion to leadframe (next to solder joint) due to different material interfaces, etc.

[0066] In order to overcome one or more of the above shortcomings, an exemplary embodiment of the invention may suppress or at least control solder bleed out of a flip chip die attach process. In particular, a flip chip solder interconnect may be provided with consistent solder volume (covering bond line thickness and bleed out zone). An exemplary embodiment provides two defined levels on the leadframe: [0067] Level 1: surface treatment for promoting soldering, [0068] Level 2: surface tuning for promoting adhesion between mold compound and leadframe.

[0069] According to an exemplary embodiment, one or more leadframe dimples or solder cavities may be formed (Level 1) in which a flip chip solder joint may be formed. Cavity or dimple finish may involve one or more of the following measures: [0070] plating (for example provision of local plating depots of tin or other solderable material) [0071] solder deposition/dispensing in form of solder paste into the cavity-provision of a bare copper surface portion [0072] pre-plating

[0073] According to another exemplary embodiment of the invention (which can be provided separately from or combined with the previously described embodiment), a proper leadframe finish (Level 2) made involve one or more of the following measures: [0074] provide a bare copper surface [0075] pre-plate with appropriate adhesion promoter material [0076] provide roughened copper or selectively roughened copper

[0077] Instead of allowing the solder die attach material to spread, the solder die attach may focus on preferred solder areas of the leadframe according to an exemplary embodiment of the invention.

[0078] It is also possible that the volume concentration of coupling material can be reached by form fitting of chip-based solder interconnect into defined leadframe positions. Advantageously, it is possible that typical variations in solder joint volume do not result in solder bleed out as the coupling material may stay inside the coupling cavity. In particular, different solder filling heights may be the consequence of different solder joint volumes. Further advantageously, a self-centering effect may be obtained during a die attach process which may ensure that a center of solder joints may be placed in the center of solder dimples or cavities. Moreover, solder joint robustness may be enhanced compared to planar solder joints (for example where a copper pillar is sitting on a planar leadframe). It is possible that one or more vertically recessed solder joints are provided (i.e. a material locking of coupling material inside a dimple), which may support the solder joint locking with the leadframe, and which may also disrupt a potential package delamination path along a planar surface.

[0079] Beyond this control of die attach solder bleed out on leadframe area, a further measure (Level 2) may allow for a defined material interface from mold compound to leadframe, which may result in consistent adhesion quality.

[0080] Exemplary embodiments of the invention can be applied in particular to the following (but also to other) flip chip (or non-flip chip) types: [0081] pillar-type (for example a copper pillar with plated pillar top) or [0082] pre-assembled with solder bumps [0083] copper pillar without solder top

[0084] According to an embodiment, a leadframe having one or more solder cavities can be manufactured, for example, by an etching and/or a stamping process.

[0085] Hence, an exemplary embodiment of the invention provides a leadframe with one or more solder dimples which may be a kind of leadframe cavity, being the pre-defined solder interconnect target area for copper pillars or solder bumps.

[0086] In an embodiment, the provision of a leadframe with one or more solder cavities can be applied to a single chip in package architecture and for a multi-chip in package configuration.

[0087] FIG. 1 illustrates a cross-section of a package 100 according to an exemplary embodiment.

[0088] The package 100 comprises an electronic chip 102, for instance a power semiconductor chip, with electric contact structures 104 for electrically contacting integrated circuit elements of the electronic chip 102 with regard to an electronic periphery. Each of the electric contact structures 104 comprises a chip pad 114. As can be taken from FIG. 1, the electronic chip 102 is mounted on a chip carrier 106 in flip chip configuration, i.e. face down. In other words, an active chip region with one or more integrated circuit elements (not shown) is located in a bottom surface of the electronic chip 102 according to FIG. 1.

[0089] Furthermore, the electrically conductive chip carrier 106, here embodied as a leadframe which consists of copper, is provided as part of the package 100 and comprises coupling cavities 108, one for each electric contact structure 104. As can be taken from FIG. 1, each of the coupling cavities 108 delimits a respective concave surface portion of the chip carrier 106. In other words, an internal contour of a border between coupling cavity 108 and chip carrier 106 is continuous which promotes undisturbed wetting of the first surface portion by solderable material (as described in the following referring to coupling structures 110).

[0090] Each of multiple coupling structures 110, here embodied as solder bumps 120 which may for instance comprise or consist of tin, is located partially in a respective coupling cavity 108 and is partially located above a respective coupling cavity 108 to extend up to the respective contact structure 104. The coupling structures 110 are hence provided for electrically contacting a respective electric contact structure 104 with the chip carrier 106 by a solder connection. As shown in FIG. 1, the coupling structures 110 partially extends beyond the respective coupling cavity 108 in both a horizontal direction and a vertical direction.

[0091] The electrically conductive chip carrier 106 has a first surface portion 122 defined by the coupling cavities 108 having a higher wettability for coupling material than an adjacent second surface portion 124 having a higher adhesiveness for material of a mold-type encapsulant 112 than the first surface portion 122. The first surface portion 122 corresponds to the concave coupling cavities 108. The second surface portion 124 of the chip carrier 106 facing the electronic chip 102 is substantially planar. The surface specific functions (promoting soldering, promoting adhesion of mold compound) can be achieved by a combination of shape, material and surface treatment of the first surface portion 122 and of the second surface portion 124.

[0092] FIG. 1 shows that the package 100 furthermore comprises the above-mentioned encapsulant 112, which may be configured as a mold compound, encapsulating the electronic chip 102 and the contact structures 104 and covering the second surface portion 124 of the chip carrier 106.

[0093] The first surface portion 122 corresponding to the coupling cavities 108 may be treated in accordance with one or more of the following surface finishes in order to specifically and locally increase wettability of the first surface portion 122 by coupling material: [0094] a solder-promoting plating, in particular comprising tin; [0095] a solder-promoting treatment of a bare metal surface, in particular a bare copper surface; and/or [0096] a solder-promoting pre-plating.

[0097] The second surface portion 124, covered by the encapsulant 112 may be equipped with a locally increased adhesiveness for material of the encapsulant 112 in accordance with one or more of the following surface finishes: [0098] an adhesiveness-promoting treatment of a bare metal surface, in particular a bare copper surface; [0099] an adhesiveness-promoting pre-plating; and/or [0100] an adhesiveness-promoting roughened surface.

[0101] In the embodiment according to FIG. 1, package 100 comprises a single electronic chip 102 embedded in a mold compound as encapsulant 112. The leadframe type chip carrier 106 has two dimples or indentations as coupling cavities 108 in a main surface thereof facing a corresponding main surface of the flip-chip type assembled electronic chip 102. The coupling structure 110 is configured as solder bump 120, but can also be a solder ball or a solder depot. As can be taken from FIG. 1, the coupling structure 110 completely fills the coupling cavities 108 thereby establishing a solder connection with the electric contact structures 104 of the electronic chip with a substantially constant cross-section in a vertical direction.

[0102] FIG. 2 to FIG. 4 illustrate cross-sections of structures obtained during carrying out a method of manufacturing a package 100 according to an exemplary embodiment.

[0103] Referring to FIG. 2, each of the electric contact structures 104 comprises a copper pillar 116 attached on a respective pad 114. Furthermore, the coupling structure 110 comprises a plated cap 118 integrally formed on the pillar 116.

[0104] FIG. 2 shows how the electronic chip 102 with copper pillars 116 bridging the pads 114 with regard to solder caps 110 are inserted into the coupling cavities 108 of the chip carrier 106 prior to soldering.

[0105] As shown in FIG. 3, a die attach procedure is then carried out by temporarily liquefying or melting the coupling structure 110, for instance by placing the arrangement according to FIG. 2 in a solder oven. Thereby, the material of the coupling structure 110 melts and reflows so as to wet a significant surface portion within the coupling cavities 108. In view of the locally increased wettability capability of the first surface portion 122 of the chip carrier 106 within the coupling cavities 108, the coupling material tends to wet a large surface area within the coupling cavities 108 and is prevented from undesirably flowing into the adjacent second surface portion 124 with intentionally poor wettability capability. As can be taken from FIG. 3, the void volume of the respective coupling cavity 108 is only partially filled with material of the coupling structure 110 and with material of pillar 116, whereas a remaining empty volume of the respective coupling cavity 108 remains even after having established the solder connection. FIG. 4 shows the structure according to FIG. 3 after molding, i.e. after encapsulating the electronic chip 102 as well as its solder connection by molds material. Thanks to the locally increased adhesiveness for encapsulant material in the second surface portion 124, a delamination-free connection between encapsulant 112 and carrier 106 in the second surface portion 124 is obtained.

[0106] FIG. 5 illustrates a cross-section of a part of a package 100 according to an exemplary embodiment.

[0107] In FIG. 5, the pronounced tendency of the coupling material to wet a large surface portion of the coupling cavity 108 can be seen particularly well. In view of the locally increased wettability, the coupling material tends to cover a large surface in the coupling cavity 108.

[0108] FIG. 6 illustrates a cross-section of an intermediate structure obtained during manufacturing a package 100 according to an exemplary embodiment.

[0109] As can be taken from FIG. 6, an upper main surface of the chip carrier 106 has been selectively roughened. For instance, the surface roughness in this selectively roughened surface portion 600, corresponding to the second surface portion 124, can be for example a microroughness and/or a nanoroughness. However, as can be taken from FIG. 6 as well, the first surface portion 122 relating to the coupling cavities 108 has not been roughened. Roughening the surface portion 600 can be accomplished for example by microetching or by plating a rough layer. The selectively roughened surface 600 only outside of the coupling cavities 108 may be obtained by firstly roughening the entire top surface of the chip carrier 106, followed by the formation of the coupling cavities 108 for example by etching so that no selective roughening procedure needs to be implemented. Thereby, the roughening procedure can be carried out in a simple and quick way.

[0110] The configuration of FIG. 6 relates to a roughened leadframe with consequently improved delamination performance. Therefore, it is possible to apply two surface finishings to the package 100 during manufacture, i.e. mold compound locking by selective surface roughening, and solder control by formation of coupling cavities 108.

[0111] As can be furthermore taken from FIG. 6, the chip carrier 106 is provided with a locking feature 155 on the lower side which may be formed for example by half etching. Locking feature 155 ensures that material of mold-type encapsulant 112 also moves under the leadframe-type chip carrier 106 (compare for instance FIG. 4), which suppresses undesired delamination of the encapsulant 112 from the chip carrier 106.

[0112] FIG. 7 illustrates a cross-section of another intermediate structure obtained during manufacturing a package 100 according to an exemplary embodiment.

[0113] In the embodiment according to FIG. 7, the coupling structure 110 located in one coupling cavity 108 electrically contacts two pillars 116 of the respective electric contact structure 104 with the chip carrier 106. The two pillars 116 per electric contact structure 104 and per coupling cavity 108 are integrally formed on a common pad 114 of the respective electric contact structure 104.

[0114] In the multiple pillar architecture per cavity according to FIG. 7, several (in the shown example two) pillars 116 are provided for a single or multi-pad 114 fitting into a single coupling cavity 108. This allows for a close standoff. Moreover, providing multiple pillars 116 for a coupling cavity 108 allows for a higher current flow during operation and/or for a better thermal heat removal.

[0115] In another embodiment, it is possible to have even more than two pillars 116 per electric contact structure 104 and per coupling cavity 108. For example, it is possible to have a two-dimensional matrix-like pattern of pillars per electric contact structure 104 and per coupling cavity 108 (see for instance FIG. 12).

[0116] FIG. 8 and FIG. 9 illustrate cross-sections of intermediate structures obtained during manufacturing a package 100 according to an exemplary embodiment.

[0117] FIG. 8 and FIG. 9 shown an architecture in which an electronic chip 102 is provided with copper pillars 116, wherein the respective coupling cavity 108 is smaller than the diameter of the pillar 116. Therefore, as shown in FIG. 8, the pillar 116 and the assigned pillar cap do not fit entirely into the coupling cavity 108 in a lateral direction. In other words, the diameter of the hemispherical pillar cap 110 may be larger than a diameter of the coupling cavity 108. As can be taken from FIG. 9, this results in a void-free filling of the coupling cavity 108 with coupling material after having established the solder connection.

[0118] FIG. 10 illustrates a cross-section of a part of a package 100 according to an exemplary embodiment.

[0119] FIG. 10 shows a detail of an electronic chip 102 with copper pillar 116 architecture after die attach, molding and singulation. According to FIG. 10, the coupling cavity 108 is closer to a full circle than a hemisphere.

[0120] FIG. 11 shows a package 100 according to yet another exemplary embodiment of the invention in which two electronic chips 102 are mounted both in flip chip architecture on a leadframe type chip carrier 106 and being solder connected using the above-described coupling cavity concept.

[0121] In addition to the above-described electronic chip 102, package 100 according to FIG. 11 hence comprises a further electronic chip 102 with further electric contact structures 104. Moreover, further coupling structures 110 are provided which are located in further coupling cavities 108 and which electrically contact the further electric contact structures 104 with the chip carrier 106 by a further solder connection. Multiple electrically conductive pillars 116 are provided, in the shown embodiment three per coupling cavity 108. FIG. 11 hence illustrates that the described coupling cavity principle is applicable to any desired number of pillars 116 per coupling cavity 108, and can be applied to a single chip-per-package architecture or a multiple chip-per-package architecture.

[0122] FIG. 12 is a plane/top view of a rectangular coupling cavity 108 and a circular coupling cavity 108 in a respective chip carrier 106 in combination with a group of parallel pillars 116 according to exemplary embodiments of the invention.

[0123] FIG. 12 illustrates that a coupling cavity 108 according to an exemplary embodiment of the invention can be implemented in very different geometrical shapes. Possible shapes are a circular perimeter, an oval perimeter, or any polygonal perimeter (such as a rectangular or even square perimeter, a hexagonal perimeter, or the like) with sharp or rounded corners.

[0124] As can be taken from FIG. 12, an array of pillars 116 may be located in each of the coupling cavities 108. Such an array may be a matrix-like arrangement with rows and columns (as shown on the left-hand side of FIG. 12), or a central pillar 116 with one or more surrounding rings of pillars 116 (shown on the right hand side of FIG. 12). Other types of pillars 116 or conductive bodies with other shape are of course possible.

[0125] FIG. 13 shows a portion of a chip carrier 106 with a coupling cavity 108 in which flux 133 has been dispensed to promote a subsequent solder connection according to an exemplary embodiment.

[0126] Dispensing or dotting one or more drops of flux 133 into a coupling cavity 108 may be carried out prior to a die attach procedure, i.e. prior to soldering a coupling structure 110 (for instance a plated cap 118 on a pillar 116 of a contact structure 104) onto a surface of the chip carrier 106 in the first surface portion 122 corresponding to coupling cavity 108. The provision of flux 133 promotes the formation of a solder connection. Highly advantageously, the concave geometry of coupling cavity 108 forces the dispensed flowable flux 133 to remain within coupling cavity 108 rather than being distributed over a wider and uncontrolled surface area of the chip carrier 106. Thus, the coupling cavity 108 holds or spatially concentrates the flux 133 without flux spreading. The flux 133 may activate the (for instance copper) surface of the chip carrier 106 and may thus function as a wetting promoter. In other words, the flux 133 may clean the copper surface to promote soldering.

[0127] FIG. 13 also illustrates a horizontal width, D, and a vertical depth, d, of the coupling cavity 108. Also a typical width, L, of pillar 116 is shown. Advantageously, horizontal width, D, may be larger than vertical depth, d. Hence, the coupling cavity/cavities 108 may be broader than deep, for instance may have a semielliptical shape in a cross-sectional view. For example, horizontal width, D, may be in a range between 20 μm and 1000 μm, in particular in a range between 50 μm and 200 μm. The actual dimension of horizontal width, D, may also depend in particular on the width, L, of pillar 116 and on the number of pillars 116 per coupling cavity 108. For instance, the width, L, of pillar 116 may be in a range between 20 μm and 200 μm, in particular between 50 μm and 150 μm. Vertical depth, d, of coupling cavity 108 may be in a range between 3 μm and 100 μm, in particular in a range between 5 μm and 30 μm. When the coupling cavity 108 becomes too shallow, some remaining solder bleed may occur. When the coupling cavity 108 becomes too deep, issues concerning chip underfill may arise.

[0128] FIG. 14 illustrates a cross-section of a structure obtained during carrying out a method of manufacturing a package 100 according to an exemplary embodiment. In the structure according to FIG. 14, a copper pillar 116 (without solder cap 118) is connected via a pad 114 to the electronic chip 102. A coupling structure 110, which may for instance be embodied as solder paste, an electrically conductive adhesive, or a sinterable material, is placed inside the cavity 108 corresponding to the first surface 122. FIG. 15 illustrates a cross-section of a part of a package 100 according to an exemplary embodiment formed based on the structure shown in FIG. 14 after die attach and molding.

[0129] It should be noted that the term “comprising” does not exclude other elements or features and the “a” or “an” does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs shall not be construed as limiting the scope of the claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.