A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The antistatic die attach material includes a mixture of a nonconductive adhesive material and carbon black or graphite. In one example, the antistatic die attach material has a resistivity between 10.sup.1 Ω.Math.cm and 10.sup.10 Ω.Math.cm.

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.

A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has amounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.

A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

A strip of semiconductor devices includes a plurality of leadframes electrically isolated from each other, a plurality of semiconductor chips, and an encapsulation material. Each leadframe has a first surface and a second surface opposite to the first surface. At least one semiconductor chip of the plurality of semiconductor chips is electrically coupled to the first surface of each leadframe. The encapsulation material encapsulates each semiconductor chip and at least portions of each leadframe.

A power semiconductor module having a pressure application body, a circuit carrier, which is embodied with a first conductor track, a power semiconductor element arranged thereon and an internal connecting device, and also having a housing which is embodied with a guide device arranged therein, with a connecting element. The connecting element is embodied as a bolt with first and second end sections and an intermediate section therebetween, wherein the first end section rests on the circuit carrier and is electrically conductively connected thereto; the second end section projects out of the housing through a cutout; and wherein the connecting element is arranged in the assigned guide device. The pressure application body has a first rigid partial body and a second elastic partial body, wherein the second partial body protrudes out of the first partial body in the direction of the housing.

Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.

A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.

Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).