A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

A semiconductor module includes: a first power semiconductor element that includes a first main current electrode; a main body that accommodates therein the first power semiconductor element; and a first main current terminal connectable to the first main current electrode. The main body includes: a top face; a side face that connects to the top face; a bottom face fixable to a cooler; and a recessed portion that is on the side face, and accommodates therein an end portion of an insulating member. The first main current terminal protrudes from the side face of the main body, and includes: a first face; and a second face on an opposite side of the first face. The second face is closer to the bottom face than the first face on the side face. The recessed portion is on the side face between the bottom face and the second face, and is at a position apart from the bottom face.

In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.

Packaged semiconductor device having a heat sink, wherein the heat sink has a top, a bottom, lateral surfaces that connect the top to the bottom, and, extending within the heat sink, a cooling structure with an inlet line as well as an outlet line for a cooling medium, and is composed of an electrically conductive material with a first coefficient of thermal expansion at the top and with a second coefficient of thermal expansion at the bottom, a die is arranged on each of the top and the bottom of the heat sink and is connected to the heat sink in an electrically conductive manner, the coefficients of thermal expansion of the top and of the bottom of the heat sink correspond in each case to the coefficient of thermal expansion of the die arranged thereon or differ from the coefficient of thermal expansion of the die arranged thereon by at most 10% or by at most 20%.

A semiconductor device includes a semiconductor element, which has a protective film having an opening that exposes a part of a source electrode and disposed/provided to position an end portion thereof on the source electrode. A rewiring layer has wiring that is connected to the source electrode and to a conductive connecting member, and an insulator that covers a part of the source wiring. The insulator includes: an insulating film having (a) an opening for exposing a part of the source wiring, and (b) an end portion of the opening provided in a facing region of the opening; and an insulating film having (c) (i) an opening for exposing a part of the source wiring having a solder arranged therein and (ii) a connecting member arranged therein.

In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

A lead frame structure of a light emitting diode includes a ceramic bed, a metal layer and a plastic seat. The metal layer has a first metal circuit area, a second metal circuit area, a gap dividing the first metal circuit area and the second metal circuit area, and a metal ring surrounding the first metal circuit area, the second metal circuit area and the gap. The plastic seat has a hollow function area. The first metal circuit area, the second metal circuit area and a part of the metal ring expose the function area to make the metal (circuit) layer of the function area has no gap to avoid excess glue. This can efficiently accomplish to increase intensity, quality and reliability of the packaged products.

A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

A semiconductor device substrate and wiring member including a first noble metal plating layer to become internal terminals is formed at predetermined sites on a metal plate, a metal plating layer is formed on the first noble metal plating layer as having a same shape as the first noble metal plating layer, a second noble metal plating layer to become external terminals is formed on a part of the metal plating layer, and a height of a surface of the second noble metal plating layer from a surface of the metal plate is larger than a height of a surface of the first noble metal plating layer from the surface of the metal plate.