A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

A packaged electronic system having a support formed by an insulating organic substrate housing a buried conductive region that is floating. A first die is fixed to the support and carries, on a first main surface, a first die contact region capacitively coupled to a first portion of the buried conductive region. A second die is fixed to the support and carries, on a first main surface, a second die contact region capacitively coupled to a second portion of the buried conductive region. A packaging mass encloses the first die, the second die, the first die contact region, the second die contact region, and, at least partially, the support.

A lead frame array for carrying chips includes a plurality of lead frames. Any four lead frames adjacent to each other and have two pairs of linking bridge groups which are connected any two lead frames adjacent to each other by one of the linking bridge groups. Each linking bridge group has an inner linking bridge, a slanted linking bridge and an outer linking bridge. An LED package structure with multiple chips is further provided, which includes a lead frame formed by cutting the lead frame array.

A structure of a substrate is provided for application in an electric power module. The substrate includes element regions, on which a plurality of semiconductor elements are arranged, a center region that defines a space among the element regions, an input terminal region, on which an input terminal for applying an electric current to the substrate is disposed, and one or more slit insulation portions that are defined to face toward sides, respectively, of the element regions adjacent to the input terminal region, which are among the element regions. The slit insulation portions extend toward the center region in such a manner that an electric current applied through the input terminal region flows into the center region.

A stem for a semiconductor package, includes a plate, a frame, positioned on an outer periphery of the plate in a plan view, and bonded to the plate, and a lead terminal held in a state insulated from the plate and the frame. The plate protrudes from a top surface and a bottom surface of the frame, and a protruding amount of the plate from the top surface and a protruding amount of the plate from the bottom surface are the same.

A magnetic sensor chip includes a magnetic sensor including a magneto-resistance element and connection terminals electrically connected to the magnetic sensor. Signal terminals are separated from the current path and are electrically connected to the connection terminals by bonding wires. A support is separated from the current path, is at a different potential from the current path, and supports the magnetic sensor chip. The magnetic sensor chip is at a position overlapping the current path when viewed in a direction in which the magnetic sensor chip and the support are arrayed.

The present disclosure is directed to a package having a die on a die pad that has a first portion and a second portion, the second portion being larger than the first portion in a first direction. The package includes a plurality of leads, where at least a first lead has a first surface coplanar with a first, lower surface of the first portion of the die pad. The first lead having a second surface that is transverse to the first surface of the first lead. The second surface being an external surface of the lead and package. The second portion of the die pad being an extension that is overlapping the first lead.

A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.

A device comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated device coupled to the first substrate. The second package includes a second substrate and a second integrated device coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.