A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.

An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode portion located outside the die bond portion; a ceramic substrate buried in the sealing resin layer; and an electronic component disposed on the die bond portion. When viewed in plan, the die bond portion and the ceramic substrate are partially overlapped to be in contact with each other, and the terminal electrode portion and the ceramic substrate are partially overlapped to be in contact with each other. The electronic component is electrically connected to the terminal electrode portion. The metal member includes a first plating layer and a second plating layer, and the average crystal grain diameter of the first plating layer is smaller than the average crystal grain diameter of the second plating layer.

A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate. A semiconductor die is flipped onto the substrate with the first die area and the second die area aligned with the first substrate area and the second substrate area of the substrate having the solder material dispensed thereon. The electrically conductive solder material thus provides electrical coupling of: the first die area and the first substrate area, and the second die area and the second substrate area.

A lead frame includes a plurality of circuit patterns which each have a die pad and an electrode terminal portion and are disposed in a band shape, a tie bar, a frame portion and a suspension lead. Cut are a connection portion between electrode terminals and the frame portion, a connection portion between the frame portion and the tie bar at both end portions in a disposition direction of circuit patterns, and a connection portion from a connection part of the frame portion with the tie bar, between the circuit patterns to a part of the frame portion extending in the disposition direction. The electrode terminal portion is bent to extend to a direction of an upper surface of a semiconductor element. The lead frame is collectively resin-sealed while exposing the tie bar and the electrode terminal portion above the tie bar.

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

An electronic component includes: a first lead frame; a second lead frame that is provided on the first lead frame; a first electronic component that is provided between the first lead frame and the second lead frame; a connection member that is provided between the first lead frame and the second lead frame; and an insulating resin that is filled between the first lead frame and the second lead frame so as to cover the first electronic component and the connection member. A first oxide film is provided on a surface of the first lead frame. A second oxide film is provided on a surface of the second lead frame. The first lead frame and the second lead frame are electrically connected to each other by the connection member.

Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material.

An integrated circuit (IC) package includes an interconnect comprising patches of unoxidized metal that are circumscribed by a region of roughened metal formed of oxidized metal. The IC package also includes a die mounted on the interconnect. The die is conductively coupled to at least a subset of the patches of unoxidized metal.