A fingerprint sensing structure includes a flexible substrate divided into a fingerprint-sensing region and a non-fingerprint-sensing region. In the non-fingerprint-sensing region, the fingerprint sensing structure includes a plurality of organic insulating layers, a wiring layer having conductive wires and at least one inorganic insulating layer, where the wiring layer is sandwiched between two organic insulating layers to render the portion of the fingerprint sensing structure corresponding to non-fingerprint-sensing region to have bending with curvature radius not larger than 2 mm. In the finger sensing region, the fingerprint sensing structure includes a thin film transistor layer and a sensing electrode layer. The thin film transistor layer includes a plurality of thin film transistors, a plurality of conductive wires respectively along a first direction and a second direction. The sensing electrode layer has a plurality of sensing electrodes to sense surface features of living organism.

A semiconductor package includes a substrate having a semiconductor chip disposed on a top surface of the substrate, a ground ring surrounding the semiconductor chip on the top surface of the substrate, a metal-post reinforced glue wall disposed on the ground ring to surround the semiconductor chip, and a molding compound disposed only inside the metal-post reinforced glue wall and covering the semiconductor chip. The metal-post reinforced glue wall comprises a magnetic or magnetizable filler so as to form an active electro-magnetic compatibility (EMC) shielding.

An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material.

A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.

A circuit structure includes a flexible substrate, an inorganic barrier layer, a first wire, a second wire, a third wire, a fourth wire, an organic dielectric layer, a first conductive via, and a second conductive via. The inorganic barrier layer is disposed over the flexible substrate. The first and second wires are disposed on the inorganic barrier layer and contact the inorganic barrier layer. The first and second wires are separated from each other. The organic dielectric layer is disposed over the first and second wires. The third wire is disposed in the organic dielectric layer. The fourth wire is disposed above the organic dielectric layer. The first conductive via is disposed in the organic dielectric layer and contacts the first and third wires. The second conductive via is disposed in the organic dielectric layer and contacts the second and fourth wires.

Provided is a wiring structural body provided with a wiring pattern including a through-wiring pattern, the wiring structural body including: a silicon substrate having a through hole in which the through-wiring pattern is disposed; an insulating layer provided on a surface of the silicon substrate including an inner surface of the through hole along at least the wiring pattern; a boron layer provided on the insulating layer along the wiring pattern; and a metal layer provided on the boron layer.

A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.

A component carrier having a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure and an array of exposed highly thermally conductive cooling structures integrally formed with the stack and defining cooling channels in between is disclosed.

A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

An electronic device includes a substrate and a circuit having a plurality of electrically-conductive components disposed on the substrate. The plurality of electrically-conductive components includes first, second and third electrically-conductive components. The third electrically-conductive component has a first end portion forming a first interface with the first electrically-conductive component and a second end portion forming a second interface with the second electrically conductive component. The first electrically-conductive component is made of a first material including a first metal. The second electrically-conductive component is made of a second material including the first metal. The third electrically-conductive component is made of a third material including a gallium-based alloy and a metallic filler. The metallic filler reduces a reactivity of the third electrically-conductive component with the first metal at the first and second interfaces, and thus minimizes deterioration of the first electrically-conductive component and the second electrically-conductive component over time.