The present invention relates to an electronic device comprising a printed substrate comprising a trace of molecular ink thereon, the molecular ink being sintered to form a conductive metal trace forming the electronic device, wherein the molecular ink is chosen from a) a flake-less printable composition of 30-60 wt % of a C.sub.8-C.sub.12 silver carboxylate, 0.1-10 wt % of a polymeric binder and balance of at least one organic solvent, all weights based on total weight of the composition; or b) a flake-less printable composition of 5-75 wt % of bis(2-ethyl-1-hexylamine) copper (II) formate, bis(octylamine) copper (II) formate or tris(octylamine) copper (II) formate, 0.25-10 wt % of a polymeric binder and balance of at least one organic solvent, all weights based on total weight of the composition.

A ceramic article. In some embodiments, the ceramic article includes a ceramic body composed of a ceramic material; and a first conductive trace, the first conductive trace having a first portion entirely within the ceramic material, the first portion having a length of 0.5 mm and transverse dimensions less than 500 microns, the ceramic material including a plurality of ceramic particles in a ceramic matrix.

According to one or more embodiments, a method of manufacturing a semiconductor device including a plurality of main circuit regions arranged in a matrix and a scribe region provided between the main circuit regions is provided. The method includes: forming a first insulating film; forming a low-k film; forming a plurality of penetrating portions penetrating through the low-k film; and forming a second insulating film under low-coverage film-forming conditions to form cavities in the plurality of through-holes.

An IGBT module with a heat dissipation structure having a specific layer thickness ratio includes a layer of IGBT chips, an upper bonding layer, a circuit layer, an insulating layer, and a heat dissipation layer. The insulating layer is disposed on the heat dissipation layer, the circuit layer is disposed on the insulating layer, the upper bonding layer is disposed on the circuit layer, and the layer of IGBT chips is disposed on the upper bonding layer. A thickness of the insulating layer is less than 0.2 mm, a thickness of the circuit layer is between 1.5 mm and 3 mm, and a thickness ratio of the circuit layer to the insulating layer is greater than or equal to 7.5:1.

Conductive thick film compositions compatible to aluminum nitride, alumina and silicon nitride substrates for microelectronic circuit application. The conductive thick film composition includes first copper powder, second copper powder, and glass component. The conductive thick film composition further includes CU.sub.2O, Ag, and at least one metal element selected from Ti, V, Zr, Mn, Cr, Co, and Sn. After firing, the conductive thick film composition exhibit improved sheet resistivity, and improved adhesion with underlying substrate.

A ceramics substrate includes: a substrate body; an electric conductor layer that is built in the substrate body; and a via that is built in the substrate body to be electrically connected to the electric conductor layer. The substrate body is made of ceramics containing aluminum oxide. The via is made of a fired body of an electric conductor paste. The electric conductor paste contains molybdenum as a main component and further contains nickel oxide, aluminum oxide, and silicon dioxide.

A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between the main circuit region and the scribe region.

An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

A ball grid array (BGA) including at least one BGA chip and a plurality of solder balls directly connected to a substrate, such as a printed circuit board (PCB), where the solder balls include an epoxy. A method for producing a BGA package including providing a BGA having a plurality of epoxy-containing solder balls, positioning the BGA on a substrate, such as a PCB, and applying heat to reflow the epoxy-containing solder balls and to create a connection between the BGA and the PCB.