Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to ta second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

A component carrier with a first component carrier structure including a first stack which has at least one first electrically conductive layer structure and at least one first electrically insulating layer structure is disclosed. The at least one first electrically conductive layer structure has a first contact element which extends up to a first contact surface of the first stack. An electrically conductive connection medium is directly connected to the first contact element at the first contact surface by filling at least one recess of the first contact element. The at least one recess having a larger dimensioned cavity delimited by a smaller dimensioned surface profile.

A ceramics substrate includes: a substrate body; an electric conductor layer that is built in the substrate body; and a via that is built in the substrate body to be electrically connected to the electric conductor layer. The substrate body is made of ceramics containing aluminum oxide. The via is made of a fired body of an electric conductor paste. The electric conductor paste contains molybdenum as a main component and further contains nickel oxide, aluminum oxide, and silicon dioxide.

The present inventive concept relates to a copper based conductive paste and its preparation method. The copper based conductive paste comprises a copolymer-copper composite comprising an imidazole-silane copolymer with partially cross-linked structure and a copper powder, a solvent, a binder and an additive. The imidazole-silane copolymer with partially cross-linked structure is introduced into the copper powder whose surface is treated by a hydrochloric acid aqueous solution and a phosphoric acid aqueous solution. The imidazole-silane copolymer is polymerized by using an imidazole monomer represented by following formula 1, a silane monomer represented by following formula 2 and a cross-linking agent.

##STR00001##

In Formula 1, X represents a hydrogen atom (H) or a methyl group (—CH.sub.3), and R.sub.1 represents a vinyl group or an allyl group.

##STR00002##

In Formula 2, Y represents a methoxy group, a 2-methoxy ethoxy group or an acetoxy group, and R.sub.2 represents a vinyl group.

A ball grid array device includes a monitoring circuit of inactive solder joints and a processor such as a field programmable gate array (FPGA) or other processor capable of determining the open or closed status of the monitoring circuit. The monitoring circuit traverses one or more of the solder joints between components being joined, such as a printed circuit board and an integrated circuit device. In certain embodiments, the inactive solder joints may be located within regions of the ball grid array that are predisposed to failure, such as at the periphery or corners of the printed circuit board, or proximate to regions that experience a broad range of operating temperatures. The failure of a solder joint within the monitoring circuit can be used to schedule maintenance of the ball grid array device prior to failure of an active solder joint.

A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.

A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.

A system and method of additively manufacturing a part including electrically conductive or static dissipating fluorine-containing polymers. The method includes depositing fluorine-containing polymer additive manufacturing material onto a build platform, selectively cross-linking portions of the deposited additive manufacturing material, and curing the selectively cross-linked portions such that the part is at least one of electrically conductive and static dissipating.

In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.