Provided is a semiconductor module that can improve the insulation properties at terminals to which electric power is supplied. A semiconductor module includes a negative electrode terminal connected to a negative electrode side of direct current power; a positive electrode terminal disposed above the negative electrode terminal and connected to a positive electrode side of the direct current power in a state where an exposed portion of the negative electrode terminal including one end of the negative electrode terminal is exposed; an insulating sheet disposed between the negative electrode terminal and the positive electrode terminal for insulation between the negative electrode terminal and the positive electrode terminal in a state where an exposed portion of the insulating sheet is exposed between the one end of the negative electrode terminal and one end of the positive electrode terminal; and a first dielectric portion formed to cover at least a corner of the one end of the positive electrode terminal, the corner being in contact with the insulating sheet.

A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.

Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in package body comprising dielectric layers and electrically conductive layers, and where an external dielectric coating, such as a solder resist coating is provided on one or both external sides of the package body. The solder resist coating is patterned to avoid inside corners, e.g. the solder resist does not extend around or between electrical contact areas and thermal pads. It is observed that in conventional solder resist coatings, during thermal cycling, cracks tend to initiate at high stress points, such as at sharp inside corners. A solder resist layout which omits inside corners, and comprises outside corners only, is demonstrated to provide significantly improved resistance to initiation and propagation of cracks. Where inside corners are unavoidable, they are appropriately radiused to reduce stress.

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

There are provided a thermosetting resin composition for a semiconductor package and a prepreg and a metal clad laminate using the same. More particularly, there are provided a thermosetting resin composition for a semiconductor package capable of improving desmear characteristics by using a cyanate based ester resin and a benzoxazine resin in a thermosetting resin composition based on an epoxy resin and improving chemical resistance by using a slurry type filler to have high heat resistance and reliability, and a prepreg and a metal clad laminate using the same.

A terminal structure includes a wiring layer, a protective insulation layer, an open portion, and a connection terminal. The protective insulation layer covers the wiring layer. The open portion extends through the protective insulation layer in a thickness-wise direction to expose part of an upper surface of the wiring layer. The connection terminal is formed on the wiring layer exposed from the open portion. The open portion includes a wall surface, a depression, and a projection. The wall surface extends downward from an upper surface of the protective insulation layer. The depression is depressed into the protective insulation layer from the wall surface toward an outer side of the open portion. The projection is formed under the depression, continuously with the depression, and projected from the depression into the open portion further inward than the wall surface in a plan view. The depression is filled with the connection terminal.

A packaged semiconductor device is provided. The packaged semiconductor device includes a semiconductor die affixed to a package substrate. A conductive connector is affixed to the package substrate. A collar is formed around a perimeter of the conductive connector at a conductive connector to package substrate transition. A reinforcement structure is embedded in the collar. The reinforcement structure substantially surrounds the conductive connector at the conductive connector to package substrate transition.

A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. Also, the first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. Also, the second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

A power module is provided with reduced power and gate loop inductance. The power module may be configured in a multi-layer manner with one or more organic substrates.

A circuit module (100) includes: a substrate (10) including a plurality of inner conductors (2); a first electronic component arranged on one main surface (S1) of the substrate (10); a first resin layer (40) provided on the one main surface (S1) and configured to seal the first electronic component; a plurality of outer electrodes (B1) provided on another main surface (S2) of the substrate (10) and including a ground electrode; a conductor film (50) provided at least on an outer surface of the first resin layer (40) and a side surface (S3) of the substrate (10) and connected to the ground electrode with at least one of the plurality of inner conductors (2) interposed therebetween; and a resin film (60).