Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a layer of dielectric material; a conductive pad at least partially on a top surface of the layer of dielectric material; and a layer of material on side surfaces of the conductive pad, wherein the layer of material does not extend onto the top surface of the layer of dielectric material. Other embodiments are also disclosed.

The present invention relates to a method for manufacturing an insulating layer for a semiconductor package which can improve reliability and have excellent heat resistance by removing pores generated in the insulating layer during manufacture of an insulating layer for a semiconductor package using magnetic characteristics, and an insulating layer for a semiconductor package obtained using the method for manufacturing the insulating layer for a semiconductor package.

The present disclosure relates to an electronic chip comprising a semiconductor substrate carrying at least one metal contact extending, within the thickness of the substrate, along at least one flank of the chip.

An integrated circuit (IC) package, comprising a die having a first set of interconnects of a first pitch, and an interposer comprising an organic substrate having a second set of interconnects of a second pitch. The interposer also includes an inorganic layer over the organic substrate. The inorganic layer comprises conductive traces electrically coupling the second set of interconnects with the first set of interconnects. The die is attached to the interposer by the first set of interconnects. In some embodiments, the interposer further comprises an embedded die. The IC package further comprises a package support having a third set of interconnects of a third pitch, and a second inorganic layer over a surface of the interposer opposite to the die. The second inorganic layer comprises conductive traces electrically coupling the third set of interconnects with the second set of interconnects.

The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.

A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.

A semiconductor device including a base, a buffer member, a frame, a lid, and a semiconductor element, is disclosed. The ceramic frame is mounted on the copper base with the molybdenum buffer member interposed therebetween. The semiconductor element is sealed in a space within the frame defined by the lid. The frame includes a top portion, a lower stage portion that is disposed below the top portion and is provided with an input electrode and an output electrode, and an upper stage portion. The upper stage portion is formed in an arrangement direction of the input electrode and the output electrode, and is formed below the top portion and above the lower stage portion. The upper stage portion includes an upper stage connection portion formed on the periphery of the lower stage portion in a direction intersecting the arrangement direction of the input electrode and the output electrode.

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

A module includes: a substrate having a first surface and a second surface opposed to each other; a component mounted on the first surface; a sealing resin that covers the first surface and the component; a shield film formed to cover an upper surface and a side surface of the sealing resin and a side surface of the substrate; and a resist film formed to cover the second surface. The resist film has a plurality of protrusions.

An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.